Kia Bazargan

According to our database1, Kia Bazargan authored at least 89 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2020
Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Parallel Unary Computing Based on Function Derivatives.
ACM Trans. Reconfigurable Technol. Syst., 2020

Hybrid Binary-Unary Hardware Accelerator.
IEEE Trans. Computers, 2020

Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Low-Cost Sorting Network Circuits Using Unary Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Time-Encoded Values for Highly Efficient Stochastic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits.
IEEE Trans. Computers, 2017

An Overview of Time-Based Computing with Stochastic Constructs.
IEEE Micro, 2017

A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2017

A memory optimized mersenne-twister random number generator.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Power and Area Efficient Sorting Networks Using Unary Processing.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Polynomial Arithmetic Using Sequential Stochastic Logic.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Polysynchronous stochastic circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Axilog: Abstractions for Approximate Hardware Design and Reuse.
IEEE Micro, 2015

Axilog: language support for approximate hardware design.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Randomness meets feedback: stochastic implementation of logistic map dynamical system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Computation on Stochastic Bit Streams Digital Image Processing Case Studies.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines.
IEEE Trans. Computers, 2014

Binary stochastic implementation of digital logic.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

IIR filters using stochastic arithmetic.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Stochastic functions using sequential logic.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Sequential logic to transform probabilities.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Case Studies of Logical Computation on Stochastic Bit Streams.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

An efficient implementation of numerical integration using logical computation on stochastic bit streams.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

The synthesis of linear Finite State Machine-based Stochastic Computational Elements.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
An Architecture for Fault-Tolerant Computation with Stochastic Logic.
IEEE Trans. Computers, 2011

FPGA placement by graph isomorphism (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A fast SPFD-based rewiring technique.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Fast and Accurate Statistical Criticality Computation Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Estimation and optimization of reliability of noisy digital circuits.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

The synthesis of combinational logic to generate probabilities.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A reconfigurable stochastic architecture for highly reliable computing.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Using randomization to cope with circuit uncertainty.
Proceedings of the Design, Automation and Test in Europe, 2009

A tileable switch module architecture for homogeneous 3D FPGAs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Physical Design for Three-Dimensional Circuits.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

FPGA Technology Mapping, Placement, and Routing.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2008

Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

FPGA family composition and effects of specialized blocks.
Proceedings of the FPL 2008, 2008

2007
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Clustering based pruning for statistical criticality computation under process variations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.
Proceedings of the FPL 2007, 2007

A generalized and unified SPFD-based rewiring technique.
Proceedings of the FPL 2007, 2007

Variation-aware routing for FPGAs.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Microarchitecture floorplanning for sub-threshold leakage reduction.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Statistical Analysis and Design of HARP FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Three-dimensional place and route for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Non-contiguous linear placement for reconfigurable fabrics.
Int. J. Embed. Syst., 2006

Defect-Tolerant FPGA Architecture Exploration.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Timing-driven partitioning-based placement for island style FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory.
J. Comput. Sci. Technol., 2005

Placement and Routing in 3D Integrated Circuits.
IEEE Des. Test Comput., 2005

HARP: hard-wired routing pattern FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

3D FPGAs: placement, routing, and architecture evaluation (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Editorial: Special issue on dynamically adaptable embedded systems.
ACM Trans. Embed. Comput. Syst., 2004

Exploring Potential Benefits of 3D FPGA Integration.
Proceedings of the Field Programmable Logic and Application, 2004

Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

2003
Timing Minimization by Statistical Timing hMetis-based Partitioning.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Incremental Placement for Timing Optimization.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Placement Method Targeting Predictability Robustness and Performance.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Linear Placement for Static / Dynamic Reconfiguration in JBits.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration.
Proceedings of the 2003 Design, 2003

Fast timing-driven partitioning-based placement for island style FPGAs.
Proceedings of the 40th Design Automation Conference, 2003

2002
Multi-objective circuit partitioning for cutsize and path-based delay minimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Statistical Timing Driven Partitioning for VLSI Circuits.
Proceedings of the 2002 Design, 2002

A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator.
Proceedings of the 39th Design Automation Conference, 2002

2001
Fast floorplanning for effective prediction and construction.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures.
Proceedings of the 38th Design Automation Conference, 2001

2000
Fast Template Placement for Reconfigurable Computing Systems.
IEEE Des. Test Comput., 2000

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.
Des. Autom. Embed. Syst., 2000

Fast Hierarchical Floorplanning with Congestion and Timing Control.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Fast and accurate estimation of floorplans in logic/high-level synthesis.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A C to Hardware/Software Compiler.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Nostradamus: a floorplanner of uncertain designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
Nostradamus: a floorplanner of uncertain design.
Proceedings of the 1998 International Symposium on Physical Design, 1998


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