Ramesh Harjani

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL.

[BibT_eX]

[DOI]

Joonho Gil

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS.

[BibT_eX]

[DOI]

Sanggeun Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Are Analytical Techniques Worthwhile for Analog IC Placement?

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

ALIGN: A System for Automating Analog Layout.

[BibT_eX]

[DOI]

Desmond A. Kirkpatrick

Parijat Mukherjee

Soner Yaldiz

IEEE Des. Test, 2021

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB.

[BibT_eX]

[DOI]

Jitesh Poojary

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers.

[BibT_eX]

[DOI]

Johan H. C. van den Heuvel

Mike Chen

Marco Berkhout

Thomas H. Lee

Robert Bogdan Staszewski

Kathleen Philips

Howard C. Luong

Vadim Ivanov

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Machine Learning Techniques in Analog Layout Automation.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Aging of Current DACs and its Impact in Equalizer Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.

[BibT_eX]

[DOI]

Juzheng Liu

Shiyu Su

Meghna Madhusudan

Mohsen Hassanpourghadi

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits.

[BibT_eX]

[DOI]

Shiva Jamali-Zavareh

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Learning from Experience: Applying ML to Analog Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

A Customized Graph Neural Network Model for Guiding Analog IC Placement.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A general approach for identifying hierarchical symmetry constraints for analog circuit layout.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Design of Low Power Integrated Radios for Emerging Standards

[BibT_eX]

[DOI]

Springer, ISBN: 978-3-030-21332-9, 2020

2019

A 0.4-1.0 GHz, 47 MHop/s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker Rejection.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators.

[BibT_eX]

[DOI]

Meghna Madhusudan

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.

[BibT_eX]

[DOI]

Desmond A. Kirkpatrick

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 2.4-GHz, Sub-1-V, 2.8-dB NF, 475-µW Dual-Path Noise and Nonlinearity Cancelling LNA for Ultra-Low-Power Radios.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS for Multi-Carrier Communications.

[BibT_eX]

[DOI]

Anindya Saha

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection.

[BibT_eX]

[DOI]

Naser Mousavi

Zhiheng Wang

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 4GHz Instantaneous Bandwidth Low Squint Phased Array Using Sub-Harmonic ILO Based Channelization.

[BibT_eX]

[DOI]

Qingrui Meng

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 5μW-5mW input power range, 0-3.5V output voltage range RF energy harvester with power-estimator-enhanced MPPT controller.

[BibT_eX]

[DOI]

Xingyi Hua

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

Time-Encoded Values for Highly Efficient Stochastic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

An Overview of Time-Based Computing with Stochastic Constructs.

[BibT_eX]

[DOI]

IEEE Micro, 2017

Low-Power Wideband Analog Channelization Filter Bank Using Passive Polyphase-FFT Techniques.

[BibT_eX]

[DOI]

Hundo Shin

IEEE J. Solid State Circuits, 2017

Integrated DC-DC converter design.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage ranges.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

CMOS energy efficient integrated radios for emerging low power standards.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

A jitter-resilient sampling technique for high-resolution ADCs in wideband RF receivers.

[BibT_eX]

[DOI]

Shiva Jamali-Zavareh

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank.

[BibT_eX]

[DOI]

Hundo Shin

Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm.

[BibT_eX]

[DOI]

Qingrui Meng

Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015

A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and Injection Locking.

[BibT_eX]

[DOI]

Mohammad Elbadry

IEEE J. Solid State Circuits, 2015

Wideband blind signal classification on a battery budget.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2015

A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

Chopper stabilized sub 1V reference voltage in 65nm CMOS.

[BibT_eX]

[DOI]

Aravindhan Rangarajan

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

3.5-0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4%.

[BibT_eX]

[DOI]

Xingyi Hua

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Design of PVT tolerant inverter based circuits for low supply voltages.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Building an on-chip spectrum sensor for cognitive radios.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2014

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A unified framework for capacitive series-parallel DC-DC converter design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/Hz.

[BibT_eX]

[DOI]

Mohammad Elbadry

Sachin Kalia

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

[BibT_eX]

[DOI]

Mark A. Ferriss

Arun Natarajan

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

2012

4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

Radio receiver techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

[BibT_eX]

[DOI]

Mark A. Ferriss

Arun Natarajan

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Fully integrated capacitive converter with all digital ripple mitigation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 5-300MHz CMOS transceiver for multi-nuclear NMR spectroscopy.

[BibT_eX]

[DOI]

Jaehyup Kim

Bruce Hammer

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-mum Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

2010

A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links.

[BibT_eX]

[DOI]

Amir Amirkhany

IEEE J. Solid State Circuits, 2010

Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%).

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs.

[BibT_eX]

[DOI]

Jie Gu

Chris H. Kim

IEEE Trans. Very Large Scale Integr. Syst., 2009

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO.

[BibT_eX]

[DOI]

Jaehyup Kim

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Millimeter-wave ICs.

[BibT_eX]

[DOI]

Alireza Shirvani Marvell

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links.

[BibT_eX]

[DOI]

Amir Amirkhany

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator.

[BibT_eX]

[DOI]

Kin-Joe Sham

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Constrained Partial Response Receivers for High-Speed Links.

[BibT_eX]

[DOI]

Jaekyun Moon

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors.

[BibT_eX]

[DOI]

Josh Wibben

IEEE J. Solid State Circuits, 2008

Modeling and synthesis of wide-band switched-resonators for VCOs.

[BibT_eX]

[DOI]

Umaikhe E. Omole

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Session 19 - Low power and non-traditional RF tranceivers.

[BibT_eX]

[DOI]

Andrea Mazzanti

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs.

[BibT_eX]

[DOI]

Liuchun Cai

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator.

[BibT_eX]

[DOI]

Kin-Joe Sham

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Understanding the Transient Behavior of Injection Locked LC Oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Gain Calibration Technique for Increased Resolution in FRC Data Converters.

[BibT_eX]

[DOI]

Frank R. Dropps

IEEE Trans. Circuits Syst. II Express Briefs, 2006

FEXT Crosstalk Cancellation for High-Speed Serial Link Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A high-efficiency CMOS +22-dBm linear power amplifier.

[BibT_eX]

[DOI]

Yongwang Ding

IEEE J. Solid State Circuits, 2005

A new noncoherent UWB impulse radio receiver.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2005

High-Speed Interconnect Technology: On-Chip and Off-Chip.

[BibT_eX]

[DOI]

Jaijeet S. Roychowdhury

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Pulse generator design for UWB IR communication systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power optimized LC VCO and mixer co-design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Process tolerant design of N-tone Sigma-Delta converters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Clocking circuits for wireline communications.

[BibT_eX]

[DOI]

Jafar Savoj

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

ΣHigh-frequency LC VCO design using capacitive degeneration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Analog/RF Physical Layer Issues For UWB Systems.

[BibT_eX]

[DOI]

Robert Sainati

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A wide tuning range VCO using capacitive source degeneration.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low power implementation of an n-tone Sigma Delta converter.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On the selection of on-chip inductors for the optimal VCO design.

[BibT_eX]

[DOI]

Yong Zhan

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Enhanced analytic noise model for RF CMOS design.

[BibT_eX]

[DOI]

Jim Koeppe

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

A CMOS high efficiency +22 dBm linear power amplifier.

[BibT_eX]

[DOI]

Yongwang Ding

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

A digital DFT technique for verifying the static performance of A/D converters.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Novel integratable notch filter implementation for 100 dB image rejection.

[BibT_eX]

[DOI]

Deepa S. Parthasarathy

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A novel noise optimization design technique for radio frequency low noise amplifiers.

[BibT_eX]

[DOI]

Anand Gopinath

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001

A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Tutorial: CMOS Analog Circuits for Wireless Communications.

[BibT_eX]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

An ISM band CMOS integrated transceiver design for wireless telemetry system.

[BibT_eX]

[DOI]

Jonghae Kim

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Power optimization of CMOS LC VCOs.

[BibT_eX]

[DOI]

Ming-Ta Hsieh

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages.

[BibT_eX]

[DOI]

Ron Balczewski

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

DFT for digital detection of analog parametric faults in SC filters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

CMOS switched-op-amp-based sample-and-hold circuit.

[BibT_eX]

[DOI]

Liang Dai

IEEE J. Solid State Circuits, 2000

Analog Circuits for Wireless Communications.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Analysis and design of low-phase-noise ring oscillators.

[BibT_eX]

[DOI]

Liang Dai

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

An IF stage design for an ASK-based wireless telemetry system.

[BibT_eX]

[DOI]

Oyvind Birkenes

Jonghae Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A universal analytic charge injection model.

[BibT_eX]

[DOI]

Yongwang Ding

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A high speed differential to single-ended amplifier for instrumentation applications.

[BibT_eX]

[DOI]

Doug Dean

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Comparison and analysis of phase noise in ring oscillators.

[BibT_eX]

[DOI]

Liang Dai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Optimal test-set generation for parametric fault detection in switched capacitor filters.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid.

[BibT_eX]

[DOI]

Kavita Nair

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A telemetry and interface circuit for piezoelectric sensors.

[BibT_eX]

[DOI]

Kavita Nair

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Digital Aetection of Analog Parametric Faults in SC Filters.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Digital detection of parametric faults in data converters.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

Pseudoduplication - An ACOB Technique for Single-Ended Circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

T5: Low-Power Design.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

System-level design for test of fully differential analog circuits.

[BibT_eX]

[DOI]

Nicholas J. Stessman

IEEE J. Solid State Circuits, 1996

Mixed-Signal Design for Test.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Dynamic Amplifiers: Settling, Slewing and Power Issues.

[BibT_eX]

[DOI]

Feng Wang

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Analog circuit observer blocks.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

The Design of Analog Self-Checking Circuits.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

A 6-Bit 50MHz Current-Subtracting Two Step Flash Converter.

[BibT_eX]

[DOI]

Andrew Cable

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Macromodeling of analog circuits for hierarchical circuit design.

[BibT_eX]

[DOI]

Jianfeng Shao

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Suppression of acoustic oscillations in hearing aids using minimum phase techniques.

[BibT_eX]

Rongtai Wang

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Dual Frequency Range Integrated Circuit Accelerometer Using Capacitive and Piezoelectric Sensing Techniques.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Acoustic feedback cancellation in hearing aids.

[BibT_eX]

[DOI]

Rongtai Wang

Proceedings of the IEEE International Conference on Acoustics, 1993

1989

OASYS: a framework for analog circuit synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988

Analog circuit synthesis and exploration in OASYS.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Analog circuit synthesis for performance in OASYS.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis.

[BibT_eX]

[DOI]