Zhiyuan Dai

According to our database, Zhiyuan Dai authored at least 8 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model.

Hang Hu, Calvin Y. Lee, Ahmed ElShater, Zhiyuan Dai, Fan Ye, Un-Ku Moon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC.

Zhiyuan Dai, Hang Hu, Yimin Wu, Fan Ye, Junyan Ren

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches.

Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

A 12bit asynchronous SAR-incremental sub-range ADC.

Manxin Li, Hang Hu, Zhiyuan Dai, Fan Ye, Junyan Ren

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation.

Hang Hu, Manxin Li, Zhiyuan Dai, Fan Ye, Junyan Ren

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique.

Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC.

Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren

Proceedings of the 12th IEEE International Conference on ASIC, 2017

An input buffer for 12bit 2GS/s ADC.

Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren

Proceedings of the 12th IEEE International Conference on ASIC, 2017