Un-Ku Moon

According to our database1, Un-Ku Moon authored at least 207 papers between 1993 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to low voltage complementary metal-oxide semiconductor mixed-signal technology".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Low-Distortion Correlated Level Shifting Sample-and-Hold Stage.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

2020
A Charge-Domain Switched-G<sub>m</sub>-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter.
IEEE J. Solid State Circuits, 2020

A 951-fs<sub>rms</sub> Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator.
IEEE J. Solid State Circuits, 2020

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier.
IEEE J. Solid State Circuits, 2019

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Cascoded Ring Amplifiers for High Speed and High Accuracy Settling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Application of Ring-Amplifiers for Low-Power Wide-Bandwidth Digital Subsampling ADC-PLL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
An Oversampling Stochastic ADC Using VCO-Based Quantizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Session 14 overview: High-resolution ADCs: Data converter subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Session 22 overview: Gigahertz data converters: Data converter subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Power Optimized Comparator Selecting Method For Stochastic ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Power Efficient SAR Algorithm for High Resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Pseudo-pseudo-differential circuits.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Session 16 overview: Gigahertz data converters.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 28 overview: Hybrid ADCs.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A highly compact wideband continuous-time transimpedance low-pass filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Voltage domain correction technique for timing skew errors in time interleaved ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A multi-path ring amplifier with dynamic biasing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.65mW 20MHz 5<sup>th</sup>-order low-pass filter with +28.8dBm IIP3 using source follower coupling.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 0.6mW 31MHz 4<sup>th</sup>-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Data converter reflections: 19 papers from the last ten years that deserve a second look.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Practical modeling of comparator metastability for conventional and LSB-first SAR ADCs.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

MDLL/PLL dual-path clock generator.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A ΔΣ ADC using an LSB-first SAR quantizer.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Selectable starting bit SAR ADC.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A single OpAmp 2<sup>nd</sup>-Order ΔΣ ADC with a double integrating quantizer.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis of metastability errors in asynchronous SAR ADCs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A VCO-based spatial averaging stochastic ADC.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information.
IEEE J. Solid State Circuits, 2014

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling.
IEEE J. Solid State Circuits, 2014

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier.
Proceedings of the Symposium on VLSI Circuits, 2014

Stochastic approximation register ADC.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Time amplifiers based on phase accumulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

LSB-first SAR ADC with bit-repeating for reduced energy consumption.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Analysis and performance trade-offs of linearity calibration for stochastic ADCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Resistive correction of low output impedance high-speed current-steering DACs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Emerging analog-to-digital converters.
Proceedings of the ESSCIRC 2014, 2014

Inherently linear time symmetric pulse width modulation.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Detection and Correction Methods for Single Event Effects in Analog to Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End.
IEEE J. Solid State Circuits, 2013

Message From the Outgoing Editor-in-Chief.
IEEE J. Solid State Circuits, 2013

New Associate Editor.
IEEE J. Solid State Circuits, 2013

Analysis of back-end flash in a 1.5b/stage pipelined ADC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Parallel gain enhancement technique for switched-capacitor circuits.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Blind background calibration of harmonic distortion based on selective sampling.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

New Associate Editors.
IEEE J. Solid State Circuits, 2012

Ring Amplifiers for Switched Capacitor Circuits.
IEEE J. Solid State Circuits, 2012

A 10-b Ternary SAR ADC With Quantization Time Information Utilization.
IEEE J. Solid State Circuits, 2012

Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques.
Proceedings of the 25th International Conference on VLSI Design, 2012

A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC.
Proceedings of the Symposium on VLSI Circuits, 2012

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers.
Proceedings of the Symposium on VLSI Circuits, 2012

A 71dB dynamic range third-order ΔΣ TDC using charge-pump.
Proceedings of the Symposium on VLSI Circuits, 2012

Little-known features of well-known creatures.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Correlated jitter sampling for jitter cancellation in pipelined TDC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

The effect of correlated level shifting on noise performance in switched capacitor circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Domino-Logic-Based ADC for Digital Synthesis.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Design-Oriented Analysis of Circuits With Equality Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Analysis of Residue Integration Sampling With Improved Jitter Immunity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer.
IEEE J. Solid State Circuits, 2011

A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer.
IEEE J. Solid State Circuits, 2011

A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Binary Access Memory: An optimized lookup table for successive approximation applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 10b Ternary SAR ADC with decision time quantization based redundancy.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Stochastic Flash Analog-to-Digital Conversion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC.
IEEE J. Solid State Circuits, 2010

An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS.
IEEE J. Solid State Circuits, 2010

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp.
IEEE J. Solid State Circuits, 2010

Continuous-Time Input Pipeline ADCs.
IEEE J. Solid State Circuits, 2010

A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

An interstage correlated double sampling technique for switched-capacitor gain stages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Pseudo-differential zero-crossing-based circuit with differential error suppression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A double-sampled path-coupled single-loop ΣΔ modulator using noise-shaped integrating quantizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

PDF folding for stochastic flash ADCs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Asynchronous CLS for Zero Crossing based Circuits.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Digital PLL With a Stochastic Time-to-Digital Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Introducing Jump-Start Tutorials.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Guest Editorial Special Issue on ISCAS 2008.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Automated Design and Optimization of Low-Noise Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers.
IEEE J. Solid State Circuits, 2009

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback.
IEEE J. Solid State Circuits, 2009

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain.
IEEE J. Solid State Circuits, 2009

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver.
IEEE J. Solid State Circuits, 2009

A 10 MS/s 11-bit 0.19 mm<sup>2</sup> Algorithmic ADC With Improved Clocking Scheme.
IEEE J. Solid State Circuits, 2009

A multiplexer-based digital passive linear counter (PLINCO).
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A continuous-time input pipeline ADC with inherent anti-alias filtering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A Note From the Editors.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Sensitivity Analysis for Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.
IEEE J. Solid State Circuits, 2008

A Wide-Tracking Range Clock and Data Recovery Circuit.
IEEE J. Solid State Circuits, 2008

A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter.
IEEE J. Solid State Circuits, 2008

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain.
IEEE J. Solid State Circuits, 2008

An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Parameter variation analysis for voltage controlled oscillators in phase-locked loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Multi-loop efficient sturdy MASH delta-sigma modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Reducing the effects of component mismatch by using relative size information.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Periodic Steady-State Analysis Augmented with Design Equality Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Noise tolerant oscillator design using perturbation projection vector analysis.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 1V downconversion filter using duty-cycle controlled bandwidth tuning.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A continuous-time input pipeline ADC.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Sub 1-V Constant G<sub>m</sub>- C Switched-Capacitor Current Source.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.
IEEE J. Solid State Circuits, 2007

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters.
IEEE J. Solid State Circuits, 2007

Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Mixed-Order Sturdy MASH Delta-Sigma Modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Considerations for Stochastic Analog-to-Digital Conversion.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Time-Shifted CDS Enhancement of Comparator-Based MDAC for Pipelined ADC Applications.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

State-of-the-art continuous-time filters from scratch.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

An Efficient Design Procedure for High-Speed Low-Power Dual-Modulus CMOS Prescalers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency.
Proceedings of the 44th Design Automation Conference, 2007

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Digitally-Enhanced Phase-Locking Circuits.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 1V 10b 30MSPS Switched-RC Pipelined ADC.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC".
IEEE J. Solid State Circuits, 2006

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning.
IEEE J. Solid State Circuits, 2006

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Dependence of LC VCO oscillation frequency on bias current.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Constant transconductance bias circuit with an on-chip resistor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The effect of switch resistance on pipelined ADC MDAC settling time.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.6V Highly Linear Switched-R-MOSFET-C Filter.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 1.6Gbps Digital Clock and Data Recovery Circuit.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A low-Voltage 10-bit CMOS DAC in 0.01-mm<sup>2</sup> die area.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A generic multilevel multiplying D/A converter for pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 10-bit algorithmic A/D converter for cytosensor application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of supply and ground noise sensitivity in ring and LC oscillators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low spur fractional-N frequency synthesizer architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Will continued process-node shrinks kill high-performance analog design?
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

Continuous-time filter design optimized for reduced die area.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

CMOS implementation of nonlinear spectral-line timing recovery in digital data-communication systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Analysis of charge-pump phase-locked loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-distortion delta-sigma topologies for MASH architectures.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An improved algorithmic ADC clocking scheme.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Jitter in high-speed serial and parallel links.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

A 0.8V accurately-tuned continuous-time filter.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Background calibration techniques for multistage pipelined ADCs with digital redundancy.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Analysis of PLL clock jitter in high-speed serial links.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Continuous-time, frequency translating, bandpass delta-sigma modulator.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An extended radix-based digital calibration technique for multi-stage ADC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation.
VLSI Design, 2002

A two-chip interface for a MEMS accelerometer.
IEEE Trans. Instrum. Meas., 2002

Digital correlation technique for the estimation and correction of DAC errors in multibit mash Delta-Sigma ADCs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

High-speed pipelined A/D converter using time-shifted CDS technique.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Area efficient CMOS charge pump circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multibit Sigma-Delta ADC with mixed-mode DAC error correction.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Low-voltage low-sensitivity switched-capacitor bandpass Sigma-Delta modulator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Efficient error-cancelling algorithmic ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A switched-capacitor DAC with analog mismatch correction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An adaptive offset cancellation mixer for direct conversion receivers in 2.4 GHz CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Improved adaptive digital compensation for cascaded ΔΣ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Digital techniques for improving the accuracy of data converters.
IEEE Commun. Mag., 1999

Capacitor mismatch error cancellation technique for a successive approximation A/D converter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mismatch-shaping serial digital-to-analog converter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low-voltage switched-capacitor circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1993
Low-distortion Continuous-time R-MOSFET-C Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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