Zhiyuan Yan

Orcid: 0000-0003-3857-6649

Affiliations:
  • Hong Kong University of Science and Technology, Guangzhou, China


According to our database1, Zhiyuan Yan authored at least 6 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Word-Level Counterexample Reduction Methods for Hardware Verification.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
CoRR, 2024

Word-Level Augmentation of Formal Proof by Learning from Simulation Traces.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Addressing Variable Dependency in GNN-based SAT Solving.
CoRR, 2023


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