Shang Liu

Orcid: 0009-0000-0057-7844

Affiliations:

Hong Kong University of Science and Technology, Hong Kong, SAR, China

According to our database¹, Shang Liu authored at least 19 papers between 2023 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses.

[BibT_eX]

[DOI]

CoRR, May, 2026

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision.

[BibT_eX]

[DOI]

CoRR, May, 2026

A New Benchmark for the Appropriate Evaluation of RTL Code Optimization.

[BibT_eX]

[DOI]

CoRR, January, 2026

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2025

Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.

[BibT_eX]

[DOI]

CoRR, 2024

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.

[BibT_eX]

[DOI]

CoRR, 2023

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Shang Liu

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