Hongce Zhang

Orcid: 0000-0003-4001-264X

According to our database1, Hongce Zhang authored at least 20 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.
CoRR, 2024

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis.
CoRR, 2024

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
CoRR, 2024

2023
r-map: Relating Implementation and Specification in Hardware Refinement Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.
CoRR, 2023

Addressing Variable Dependency in GNN-based SAT Solving.
CoRR, 2023

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021
Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2021

Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Pono: A Flexible and Extensible SMT-Based Model Checker.
Proceedings of the Computer Aided Verification - 33rd International Conference, 2021

2020
Synthesizing Environment Invariants for Modular Hardware Verification.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2020

In Search for a SAT-friendly Binarized Neural Network Architecture.
Proceedings of the 8th International Conference on Learning Representations, 2020

Verification of Recurrent Neural Networks for Cognitive Tasks via Reachability Analysis.
Proceedings of the ECAI 2020 - 24th European Conference on Artificial Intelligence, 29 August-8 September 2020, Santiago de Compostela, Spain, August 29 - September 8, 2020, 2020

2019
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification.
ACM Trans. Design Autom. Electr. Syst., 2019

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2019

2018
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification.
Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

2016
A hardware-based technique for efficient implicit information flow tracking.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016


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