Wenji Fang

Orcid: 0000-0002-8380-9395

According to our database1, Wenji Fang authored at least 8 papers between 2023 and 2024.

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Bibliography

2024
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.
CoRR, 2024

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR, 2024

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
CoRR, 2024

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model.
CoRR, 2024

2023
r-map: Relating Implementation and Specification in Hardware Refinement Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.
CoRR, 2023

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023


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