Abdel Ejnioui

According to our database, Abdel Ejnioui authored at least 40 papers between 1995 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics.

Rawad N. Al-Haddad, Rashad S. Oreifej, Ramtin Zand, Abdel Ejnioui, Ronald F. DeMara

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

2013

A stochastic approach for evaluating quality of service in wireless cellular networks.

Abdel Ejnioui, Carlos E. Otero, Ivica Kostanic

Int. J. Wirel. Mob. Comput., 2013

Prioritisation of software requirements using grey relational analysis.

Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero

Int. J. Comput. Appl. Technol., 2013

System analysis methods in emergency systems.

Jeffrey A. McDougall, Luis Daniel Otero, Juan Avendano, Abdel Ejnioui

Proceedings of the IEEE International Systems Conference, 2013

A support vector machine for terrain classification in on-demand deployments of wireless sensor networks.

Rana Haber, Adrian M. Peter, Carlos E. Otero, Ivica Kostanic, Abdel Ejnioui

Proceedings of the IEEE International Systems Conference, 2013

Engineering graphic user interfaces with protected content.

Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi

Proceedings of the IEEE International Systems Conference, 2013

Formalizing the design of embedded software using sequence diagrams and abstract state machines.

Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi

Proceedings of the 2nd annual conference on Research in information technology, 2013

2012

A simulation-based fuzzy multi-attribute decision making for prioritizing software requirements.

Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero

Proceedings of the 1st Annual conference on Research in information technology, 2012

2011

Evaluation of Information Security Controls in Organizations by Grey Relational Analysis.

Angel R. Otero, Abdel Ejnioui, Carlos E. Otero, Gurvirender Tejay

Int. J. Dependable Trust. Inf. Syst., 2011

2009

Runtime Adaptation in Reconfigurable System-on-Chips.

Abdel Ejnioui

Proceedings of the ICPPW 2009, 2009

2008

A Parallel Array to Accelerate GFA Modeling in Video Coding.

Abdel Ejnioui, Paul Bao

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

A parallel architecture for GFA modeling in video coding.

Abdel Ejnioui, Paul Bao

Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2007

Tiered Algorithm for Distributed Process Quiescence and Termination Detection.

Ronald F. DeMara, Yili Tseng, Abdel Ejnioui

IEEE Trans. Parallel Distributed Syst., 2007

FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.

Abdel Ejnioui

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Hardware Architectures for the Generalized Finite Automata Algorithm.

Abdel Ejnioui, Paul Bao

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Prototyping of a Two-Phase Micropipeline on FPGAs.

Abdel Ejnioui

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Hardware Acceleration of the Generalized Finite Automata Algorithm.

Abdel Ejnioui, Paul Bao

Proceedings of the 2007 International Conference on Computer Design, 2007

2006

Clockless Pipelining for Coarse Grain Datapaths.

Abdelhalim Alsharqawi, Abdel Ejnioui

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Synthesis of Pipelined SRSL Circuits.

Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.

Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Pipelining of double precision floating point division and square root operations.

Anuja Jayraj Thakkar, Abdel Ejnioui

Proceedings of the 44st Annual Southeast Regional Conference, 2006

2005

Synthesis of Self-Resetting Stage Logic Pipelines.

Abdelhalim Alsharqawi, Abdel Ejnioui

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Pipeline synthesis of SRSL circuits.

Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui

Proceedings of the 12th IEEE International Conference on Electronics, 2005

SRSL pipelining of coarse-grain datapaths.

Abdelhalim Alsharqawi, Abdel Ejnioui

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices.

Abdel Ejnioui, Ronald F. DeMara

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004

Control and Data Flow Graph Extraction for High-Level Synthesis.

Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A Reconfigurable Memory Management Core for Java Applications.

Abdel Ejnioui, Abdelkader Rhiati

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Pipeline Design Based on Self-Resetting Stage Logic.

Abdel Ejnioui, Abdelhalim Alsharqawi

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Self-resetting stage logic pipelines.

Abdel Ejnioui, Abdelhalim Alsharqawi

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Pipeline-Level Control of Self-Resetting Pipelines.

Abdel Ejnioui, Abdelhalim Alsharqawi

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

Routing on field-programmable switch matrices.

Abdel Ejnioui, N. Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2003

Multiterminal net routing for partial crossbar-based multi-FPGA systems.

Abdel Ejnioui, N. Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2003

Supply Voltage Scalable System Design Using Self-Timed Circuits.

W. Kuang, J. S. Yuan, Abdel Ejnioui

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2002

A VLSI Architecture for Object Recognition Using Tree Matching.

K. Sitaraman, N. Ranganathan, Abdel Ejnioui

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001

A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.

Abdel Ejnioui, N. Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2001

2000

Routing on Switch Matrix Multi-FPGA Systems.

Abdel Ejnioui, N. Ranganathan

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Design Partitioning on Single-Chip Emulation Systems.

Abdel Ejnioui, N. Ranganathan

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A tree-matching chip.

Vamsi Krishna, N. Ranganathan, Abdel Ejnioui

IEEE Trans. Very Large Scale Integr. Syst., 1999

Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.

Abdel Ejnioui, N. Ranganathan

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1995

Systolic algorithms for tree pattern matching.

Abdel Ejnioui, N. Ranganathan

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995