We stand with Ukraine  

Adarsh Patil

Orcid: 0000-0001-9533-6997

Affiliations:
  • Arm, Cambridge, UK
  • University of Edinburgh, UK (former)
  • Indian Institute of Sciences, Bangalore, India (former)


According to our database1, Adarsh Patil authored at least 6 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Improving compiler support for SIMD offload using Arm Streaming SVE.
[BibTeX]
[DOI]
Mohamed Husain Noor Mohamed
,
Adarsh Patil
,
Latchesar Ionkov
,
Eric Van Hensbergen
CoRR, June, 2025

2024
UDON: A case for offloading to general purpose compute on CXL memory.
[BibTeX]
[DOI]
Jon Hermes
,
Josh Minor
,
Minjun Wu
,
Adarsh Patil
,
Eric Van Hensbergen
CoRR, 2024

2023
Āpta: Fault-tolerant object-granular CXL disaggregated memory for accelerating FaaS.
[BibTeX]
[DOI]
Adarsh Patil
,
Vijay Nagarajan
,
Nikos Nikoleris
,
Nicolai Oswald
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Network, 2023

2021
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication.
[BibTeX]
[DOI]
Adarsh Patil
,
Vijay Nagarajan
,
Rajeev Balasubramonian
,
Nicolai Oswald
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache.
[BibTeX]
[DOI]
Adarsh Patil
CoRR, 2020

2017
HAShCache: Heterogeneity-Aware Shared DRAMCache for Integrated Heterogeneous Systems.
[BibTeX]
[DOI]
Adarsh Patil
,
Ramaswamy Govindarajan
ACM Trans. Archit. Code Optim., 2017


  Loading...