Rajeev Balasubramonian
Orcid: 0009-0009-4093-5904Affiliations:
- University of Utah, Salt Lake City, Utah, USA
According to our database1,
Rajeev Balasubramonian
authored at least 89 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on cs.utah.edu
On csauthors.net:
Bibliography
2023
IEEE Micro, 2023
2022
IEEE Trans. Knowl. Data Eng., 2022
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion.
IEEE Micro, 2022
Efficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract).
Proceedings of the 38th IEEE International Conference on Data Engineering, 2022
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
2019
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01763-6, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
2018
IEEE Micro, 2018
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2018
Proceedings of the 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2018
VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
ACM Trans. Archit. Code Optim., 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
2014
IEEE Micro, 2014
Proceedings of the International Conference for High Performance Computing, 2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller.
Proceedings of the HASP 2014, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
Int. J. Parallel Program., 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Optimizing datacenter power with memory system levers for guaranteed quality-of-service.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01734-6, 2011
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality.
Proceedings of the Computer Architecture, 2010
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
Handling the problems and opportunities posed by multiple on-chip memory controllers.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
ACM SIGOPS Oper. Syst. Rev., 2009
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the 16th International Conference on High Performance Computing, 2009
2008
IEEE Micro, 2008
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
J. Instr. Level Parallelism, 2007
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
2006
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
2005
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
Proceedings of the 18th Annual International Conference on Supercomputing, 2004
2003
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003
2002
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001
2000
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000