Rajeev Balasubramonian

Affiliations:
  • University of Utah, Salt Lake City, Utah, USA


According to our database1, Rajeev Balasubramonian authored at least 82 papers between 2000 and 2021.

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Bibliography

2021
OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Compact Leakage-Free Support for Integrity and Reliability.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Innovations in the Memory System
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2019

GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Wire-Aware Architecture and Dataflow for CNN Accelerators.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

The POP Detector: A Lightweight Online Program Phase Detection Framework.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

ρ: Relaxed Hierarchical ORAM.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
IEEE Micro, 2018

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration.
CoRR, 2018

An MLP-aware leakage-free memory controller.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Secure DIMM: Moving ORAM Primitives Closer to Memory.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories.
ACM Trans. Archit. Code Optim., 2017

INXS: Bridging the throughput and energy gap for spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Introspective Computing.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Near-Data Processing [Guest editors' introduction].
IEEE Micro, 2016

Addressing service interruptions in memory with thread-to-rank assignment.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Efficiently prefetching complex address patterns.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Avoiding information leakage in the memory controller with fixed service policies.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Improving memristor memory with sneak current sharing.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Fixed-function hardware sorting accelerators for near data MapReduce execution.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Overcoming the challenges of crossbar resistive memory architectures.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads.
IEEE Micro, 2014

Near-Data Processing: Insights from a MICRO-46 Workshop.
IEEE Micro, 2014

Managing DRAM Latency Divergence in Irregular GPGPU Applications.
Proceedings of the International Conference for High Performance Computing, 2014

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller.
Proceedings of the HASP 2014, 2014

MemZip: Exploring unconventional benefits from memory compression.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Managing Data Placement in Memory Systems with Multiple Memory Controllers.
Int. J. Parallel Program., 2012

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Efficient scrub mechanisms for error-prone emerging memories.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Optimizing datacenter power with memory system levers for guaranteed quality-of-service.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Multi-Core Cache Hierarchies
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2011

Buses and Crossbars.
Proceedings of the Encyclopedia of Parallel Computing, 2011

CHOP: Integrating DRAM Caches for CMP Server Platforms.
IEEE Micro, 2011

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Prediction Based DRAM Row-Buffer Management in the Many-Core Era.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Hardware prediction of OS run-length for fine-grained resource customization.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

Rethinking DRAM design and organization for energy-constrained multi-cores.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality.
Proceedings of the Computer Architecture, 2010

Towards scalable, energy-efficient, bus-based on-chip networks.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

CHOP: Adaptive filter-based DRAM caching for CMP server platforms.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Micro-pages: increasing DRAM efficiency with locality-aware data placement.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

SWEL: hardware cache coherence protocols to map shared data onto shared caches.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

Handling the problems and opportunities posed by multiple on-chip memory controllers.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
OS execution on multi-cores: is out-sourcing worthwhile?
ACM SIGOPS Oper. Syst. Rev., 2009

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Non-uniform power access in large caches with low-swing wires.
Proceedings of the 16th International Conference on High Performance Computing, 2009

2008
Architecting Efficient Interconnects for Large Caches with CACTI 6.0.
IEEE Micro, 2008

Scalable and reliable communication for hardware transactional memory.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
Power Efficient Approaches to Redundant Multithreading.
IEEE Trans. Parallel Distributed Syst., 2007

Understanding the Impact of 3D Stacked Layouts on ILP.
J. Instr. Level Parallelism, 2007

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Leveraging 3D Technology for Improved Reliability.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Interconnect design considerations for large NUCA caches.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Leveraging Wire Properties at the Microarchitecture Level.
IEEE Micro, 2006

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Interconnect-Aware Coherence Protocols for Chip Multiprocessors.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004

2003
A Dynamically Tunable Memory Hierarchy.
IEEE Trans. Computers, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Reducing the complexity of the register file in dynamic superscalar processors.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Dynamically allocating processor resources between nearby and distant ILP.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000


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