Agustín Fernández

According to our database1, Agustín Fernández authored at least 19 papers between 1991 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2015
In-flight reconfigurable FPGA-based space systems.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2011
A take-home exam to assess professional skills.
Proceedings of the 2011 Frontiers in Education Conference, 2011

2010
A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization.
Vis. Comput., 2010

2006
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Workload Characterization of 3D Games.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

2005
Shader Performance Analysis on a Modern GPU Architecture.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

A Single (Unified) Shader GPU Microarchitecture for Embedded Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005

2003
A Cost-Effective Implementation of Multilevel Tiling.
IEEE Trans. Parallel Distributed Syst., 2003

2002
Register tiling in nonrectangular iteration spaces.
ACM Trans. Program. Lang. Syst., 2002

2000
On the Performance of Hand vs. Automatically Optimized Numerical Codes.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1998
Loop bounds computation for multilevel tiling.
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

A General Algorithm for Tiling the Register Level.
Proceedings of the 12th international conference on Supercomputing, 1998

Performance Evaluation of Tiling for the Register Level.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1996
A Unified Transformation Technique for Multilevel Blocking.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
Loop Transformation Using Nonunimodular Matrices.
IEEE Trans. Parallel Distributed Syst., 1995

1992
Scheduling partitions in systolic algorithms.
Proceedings of the Application Specific Array Processors, 1992

1991
Performance evaluation of transputer systems with linear algebra problems.
Microprocessing and Microprogramming, 1991

Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors.
Proceedings of the Distributed Memory Computing, 2nd European Conference, 1991

Transformation of systolic algorithms for interleaving partitions.
Proceedings of the Application Specific Array Processors, 1991


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