Roger Espasa

According to our database, Roger Espasa authored at least 40 papers between 1995 and 2021.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2021

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2010

A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization.

Jordi Roca, Victor Moya Del Barrio, Carlos González, Vicente Escandell, Albert Murciego, Agustín Fernández, Roger Espasa

Vis. Comput., 2010

Larrabee: A Many-Core Intel Architecture for Visual Computing.

Roger Espasa

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

2009

Larrabee: A Many-Core x86 Architecture for Visual Computing.

Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan

IEEE Micro, 2009

2006

ATTILA: a cycle-level execution-driven simulator for modern GPU architectures.

Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa

Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Workload Characterization of 3D Games.

Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustín Fernández, Roger Espasa

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

2005

Conflict-Free Accesses to Strided Vectors on a Banked Cache.

André Seznec, Roger Espasa

IEEE Trans. Computers, 2005

Shader Performance Analysis on a Modern GPU Architecture.

Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

A Single (Unified) Shader GPU Microarchitecture for Embedded Systems.

Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa

Proceedings of the High Performance Embedded Architectures and Compilers, 2005

2004

Link-Time Path-Sensitive Memory Redundancy Elimination.

Manel Fernández, Roger Espasa

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies.

Manel Fernández, Roger Espasa

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003

A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications.

Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero

Theory Comput. Syst., 2003

Load redundancy elimination on executable code.

Manel Fernández, Roger Espasa, Saumya K. Debray

Concurr. Comput. Pract. Exp., 2003

2002

Asim: A Performance Model Framework.

Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan

Computer, 2002

Three-dimensional memory vectorization for high bandwidth media memory systems.

Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Tarantula: A Vector Extension to the Alpha Architecture.

Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Speculative Alias Analysis for Executable Code.

Manel Fernández, Roger Espasa

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

DLP + TLP Processors for the Next Generation of Media Workloads.

Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Topic 08+13: Instruction-Level Parallelism and Computer Architecture.

Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

On the Efficiency of Reductions in µ-SIMD Media Extensions.

Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

1999

A Simulation Study of Decoupled Vector Architectures.

Roger Espasa, Mateo Valero

J. Supercomput., 1999

MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications.

Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

Exploiting a New Level of DLP in Multimedia Applications.

Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Adding a vector unit to a superscalar processor.

Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Registers Size Influence on Vector Architectures.

Luis Villa, Roger Espasa, Mateo Valero

Proceedings of the Vector and Parallel Processing, 1998

An ISA Comparison Between Superscalar and Vector Processors.

Francisca Quintana, Roger Espasa, Mateo Valero

Proceedings of the Vector and Parallel Processing, 1998

Effective usage of vector registers in decoupled vector architectures.

Luis Villa, Roger Espasa, Mateo Valero

Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

A case for merging the ILP and DLP paradigms.

Francisca Quintana, Roger Espasa, Mateo Valero

Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes.

Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

A Performance Study of Out-of-order Vector Architectures and Short Registers.

Luis Villa, Roger Espasa, Mateo Valero

Proceedings of the 12th international conference on Supercomputing, 1998

Vector Architectures: Past, Present and Future.

Roger Espasa, Mateo Valero, James E. Smith

Proceedings of the 12th international conference on Supercomputing, 1998

Command Vector Memory Systems: High Performance at Low Cost.

Jesús Corbal, Roger Espasa, Mateo Valero

Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997

Exploiting instruction- and data-level parallelism.

Roger Espasa, Mateo Valero

IEEE Micro, 1997

Out-of-Order Vector Architectures.

Roger Espasa, Mateo Valero, James E. Smith

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

A Victim Cache for Vector Registers.

Roger Espasa, Mateo Valero

Proceedings of the 11th international conference on Supercomputing, 1997

Multithreaded Vector Architectures.

Roger Espasa, Mateo Valero

Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance.

Roger Espasa, Mateo Valero

Proceedings of the Fourth International on High-Performance Computing, 1997

Effective Usage of Vector Registers in Advanced Vector Architectures.

Luis Villa, Roger Espasa, Mateo Valero

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

Decoupled Vector Architectures.

Roger Espasa, Mateo Valero

Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

1995

Quantitative analysis of vector code.

Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé

Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995