David Merodio Codinachs

According to our database, David Merodio Codinachs authored at least 22 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA.

Felipe Viel, Kleber R. Gouveia, Edilberto Costa, Márcio Oliveira, Miguel Boing, André Martins Pio de Mattos, Gabriel Mariano Marcelino, David Merodio Codinachs, Laio Oriel Seman, Eduardo Augusto Bezerra

IEEE Embed. Syst. Lett., June, 2023

PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs.

Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs, Filomena Decuzzi

Proceedings of the 19th International Conference on Synthesis, 2023

EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications.

Ludovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer, Sergio A. Pertuz, Lester Kalms, Cornelia Wulf, Najdet Charaf, Luca Sterpone, Sarah Azimi, Daniele Rizzieri, Salvatore Gabriele La Greca, David Merodio Codinachs, Stephen King

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices.

Andrea Portaluri, Sarah Azimi, Corrado De Sio, Luca Sterpone, David Merodio Codinachs

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process.

Corrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks.

Vasileios Leon, Ioannis Stamoulias, George Lentaris, Dimitrios Soudris, David González Arjona, Ruben Domingo, David Merodio Codinachs, Isabelle Conway

IEEE Access, 2021

2019

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs.

Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, Raoul Grimoldi, L. Cattaneo

Integr., 2019

2018

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs.

Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, L. Cattaneo

Proceedings of the 15th International Conference on Synthesis, 2018

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs.

Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA.

Konstantinos Maragos, Vasileios Leon, George Lentaris, Dimitrios Soudris, David González Arjona, Ruben Domingo, Antonio Pastor, David Merodio Codinachs, Isabelle Conway

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

BRAVE NG-MEDIUM FPGA reconfiguration through SpaceWire: example use case and performance analysis.

Klemen Bravhar, Victor Martins, Lucana Santos, David Merodio Codinachs

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017

Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs.

Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs, Raoul Grimoldi

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Analysis of radiation-induced SEUs on dynamic reconfigurable systems.

Luca Sterpone, Luca Boragno, David Merodio Codinachs

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs.

Boyang Du, Luca Sterpone, David Merodio Codinachs

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs.

Boyang Du, Luca Sterpone, Lorenzo Venditti, David Merodio Codinachs

Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

In-flight reconfigurable FPGA-based space systems.

Norma Montealegre, David Merodio, Agustín Fernández, Philippe Armbruster

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs.

Marco Desogus, Luca Sterpone, David Merodio Codinachs

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013

Guest Editors' introduction: Special section on adaptive hardware and systems.

Khaled Benkrid, Didier Keymeulen, Umeshkumar D. Patel, David Merodio Codinachs

IEEE Trans. Computers, 2013

A fully-automated flow for ITAR-free rad-hard Atmel FPGAs.

Nikos Andrikos, Massimo Violante, David Merodio Codinachs

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Preface.

Khaled Benkrid, Didier Keymeulen, David Merodio, Michael Newell, Rainer Wansch, Umeshkumar D. Patel, Ahmet T. Erdogan, Niels Hadaschik, Luca Sterpone, Jelle Poupaert, Massimo Violante

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2011

A reliable fault classifier for dependable systems on SRAM-based FPGAs.

Cristiana Bolchini, Chiara Sandionigi, Luca Fossati, David Merodio Codinachs

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010

A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms.

Cristiana Bolchini, Luca Fossati, David Merodio Codinachs, Antonio Miele, Chiara Sandionigi

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010