Ahmad Darabiha

According to our database1, Ahmad Darabiha authored at least 9 papers between 2003 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2008
Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Power Reduction Techniques for LDPC Decoders.
IEEE J. Solid State Circuits, 2008

2007
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.
Mach. Vis. Appl., 2006

A bit-serial approximate min-sum LDPC decoder and FPGA implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
FPGA-based supercomputing: an implementation for molecular dynamics.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Reconfigurable Molecular Dynamics Simulator.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Video-Rate Stereo Depth Measurement on Programmable Hardware.
Proceedings of the 2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2003), 2003


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