Jonathan Rose

Moshe Eizenman

Sensors, 2020

Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Pattern Recognition, 2020

2018

High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2018

SmartEye: An Accurate Infrared Eye Tracking System for Smartphones.

[BibT_eX]

[DOI]

Braiden Brousseau

Moshe Eizenman

Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

Automatic Topology Optimization for FPGA Interconnect Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Synchronization Constraints for Interconnect Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Energy efficient object detection on the mobile GP-GPU.

[BibT_eX]

[DOI]

Fitsum Assamnew Andargie

Todd M. Austin

Valeria Bertacco

Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017

2016

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2016

Fine-Grained Interconnect Synthesis.

[BibT_eX]

[DOI]

David Biancolin

ACM Trans. Reconfigurable Technol. Syst., 2016

High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015

Automatic FPGA system and interconnect construction with multicast and customizable topology.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Performance characterization of mobile GP-GPUs.

[BibT_eX]

[DOI]

Fitsum Assamnew Andargie

Proceedings of the AFRICON 2015, Addis Ababa, Ethiopia, September 14-17, 2015, 2015

2014

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

VTR 7.0: Next Generation Architecture and CAD System for FPGAs.

[BibT_eX]

[DOI]

Konstantin Nasartschuk

ACM Trans. Reconfigurable Technol. Syst., 2014

Towards interconnect-adaptive packing for FPGAs.

[BibT_eX]

[DOI]

Jason Luu

Jason Helge Anderson

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

On Hard Adders and Carry Chains in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

Efficient methods for out-of-order load/store execution for high-performance soft processors.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012

Portable, Flexible, and Scalable Soft Vector Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Portable and scalable FPGA-based acceleration of a direct linear system solver.

[BibT_eX]

[DOI]

Wei Zhang

ACM Trans. Reconfigurable Technol. Syst., 2012

An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection.

[BibT_eX]

[DOI]

Braiden Brousseau

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

On the difficulty of pin-to-wire routing in FPGAs.

[BibT_eX]

[DOI]

Niyati Shah

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

The VTR project: architecture and CAD for FPGAs from verilog to routing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

A new, fast algorithm for detecting protein coevolution using maximum compatible cliques.

[BibT_eX]

[DOI]

Alexandr Bezginov

Elisabeth R. M. Tillier

Algorithms Mol. Biol., 2011

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop.

[BibT_eX]

[DOI]

Guy G. Lemieux

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect.

[BibT_eX]

[DOI]

Jason Luu

Jason Helge Anderson

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters.

[BibT_eX]

[DOI]

Peter A. Jamieson

IEEE Trans. Very Large Scale Integr. Syst., 2010

Faster coevolution detection of proteins using maximum similar cliques.

[BibT_eX]

[DOI]

Alexandr Bezginov

Elisabeth R. M. Tillier

Proceedings of the First ACM International Conference on Bioinformatics and Computational Biology, 2010

2009

Data parallel FPGA workloads: Software versus hardware.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

The evolution of architecture exploration of programmable devices.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

Fine-grain performance scaling of soft vector processors.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Compilers, 2009

2008

Area and delay trade-offs in the circuit and architecture design of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Modeling routing demand for early-stage FPGA architecture development.

[BibT_eX]

[DOI]

Wei Mark Fang

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Automated transistor sizing for FPGA architecture exploration.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

VESPA: portable, scalable, and flexible FPGA-based vector processors.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Compilers, 2008

2007

Exploration and Customization of FPGA-Based Soft Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Measuring the Gap Between FPGAs and ASICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

FPGA Architecture: Survey and Challenges.

[BibT_eX]

[DOI]

Russell Tessier

Found. Trends Electron. Des. Autom., 2007

Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters.

[BibT_eX]

[DOI]

Peter Jamieson

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006

Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm.

[BibT_eX]

[DOI]

Ahmad Darabiha

W. James MacLean

Mach. Vis. Appl., 2006

Invited Keynote 1: Closing the gap between FPGAs and ASICs.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Application-specific customization of soft processor microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth.

[BibT_eX]

Joshua Fender

David R. Galloway

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Verilog RTL Synthesis Tool for Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Peter Jamieson

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

The Stratix II logic and routing architecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Design, layout and verification of an FPGA using automated tools.

[BibT_eX]

[DOI]

Aaron Egier

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

The microarchitecture of FPGA-based soft processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Compilers, 2005

2004

The effect of LUT and cluster size on deep-submicron FPGA performance and density.

[BibT_eX]

[DOI]

Elias Ahmed

IEEE Trans. Very Large Scale Integr. Syst., 2004

Synthetic circuit generation using clustering and iteration.

[BibT_eX]

[DOI]

Paul D. Kundarewich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Hard vs. Soft: The Central Question of Pre-Fabricated Silicon.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Hardware Accelerated Novel Protein Identification.

[BibT_eX]

[DOI]

Anish Alex

Ruth Isserlin-Weinberger

Christopher W. V. Hogue

Proceedings of the Field Programmable Logic and Application, 2004

Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.

[BibT_eX]

[DOI]

Aaron Egier

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A synthesis oriented omniscient manual editor.

[BibT_eX]

[DOI]

Tomasz S. Czajkowski

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003

A parameterized automatic cache generator for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

A high-speed ray tracing engine built on a field-programmable system.

[BibT_eX]

[DOI]

Joshua Fender

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Automatic transistor and physical design of FPGA tiles from an architectural specification.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

The Stratix<sup>TM</sup> routing and logic architecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Video-Rate Stereo Depth Measurement on Programmable Hardware.

[BibT_eX]

[DOI]

Ahmad Darabiha

W. James MacLean

Proceedings of the 2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2003), 2003

Architecture of datapath-oriented coarse-grain logic and routing for FPGAs.

[BibT_eX]

[DOI]

David M. Lewis

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Automatic generation of synthetic sequential benchmark circuits.

[BibT_eX]

[DOI]

Derek G. Corneil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Synthesizing datapath circuits for FPGAs with emphasis on area minimization.

[BibT_eX]

[DOI]

David M. Lewis

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.

[BibT_eX]

[DOI]

William Chow

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Nearest neighbour interconnect architecture in deep submicron FPGAs.

[BibT_eX]

[DOI]

Ajay Roopchansingh

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Structural analysis and generation of synthetic digital circuits with memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Mixing buffers and pass transistors in FPGA routing architectures.

[BibT_eX]

[DOI]

Mike Sheng

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Panel: (When) Will FPGAs Kill ASICs?

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Speed and area tradeoffs in cluster-based FPGA architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

A novel and efficient routing architecture for multi-FPGA systems.

[BibT_eX]

[DOI]

Mohammed A. S. Khalid

IEEE Trans. Very Large Scale Integr. Syst., 2000

Real-time, frame-rate face detection on a configurable hardware system (poster abstract).

[BibT_eX]

[DOI]

Rob McCready

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Timing-driven placement for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Automatic generation of FPGA routing architectures from high-level descriptions.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999

The memory/logic interface in FPGAs with large embedded memory arrays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

The design of an SRAM-based field-programmable gate array. I. Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Applications of clone circuits to issues in physical-design.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Equivalence classes of clone circuits for physical-design benchmarking.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Mohammed A. S. Khalid

Proceedings of the Parallel and Distributed Processing, 1999

Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs.

[BibT_eX]

[DOI]

Yaska Sankar

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Architecture and CAD for Deep-Submicron FPGAS

[BibT_eX]

[DOI]

The Springer International Series in Engineering and Computer Science 497, Kluwer, ISBN: 978-1-4615-5145-4, 1999

1998

The Transmogrifier-2: a 1 million gate rapid-prototyping system.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Effect of the prefabricated routing track distribution on FPGA area-efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Characterization and parameterized generation of synthetic combinational benchmark circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

How Much Logic Should Go in an FPGA Logic Block?

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1998

A Fast Routability-Driven Router for FPGAs.

[BibT_eX]

[DOI]

Jordan S. Swartz

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Constraints from Hell: How to Tell Makes a Good FPGA (Panel).

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Mohammed A. S. Khalid

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997

VPR: A new packing, placement and routing tool for FPGA research.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays.

[BibT_eX]

[DOI]

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond.

[BibT_eX]

[DOI]

Dwight D. Hill

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

Generation of Synthetic Sequential Benchmark Circuits.

[BibT_eX]

[DOI]

Derek G. Corneil

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996

FPGA and CPLD Architectures: A Tutorial.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1996

Directional bias and non-uniformity in FPGA global routing architectures.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Characterization and Parameterized Random Generation of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Architecture of Centralized Field-Configurable Memory.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Using Architectural "Families" to Increase FPGA Speed and Density.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Definition and solution of the memory packing problem for field-programmable systems.

[BibT_eX]

[DOI]

David Karchmer

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

A stochastic model to predict the routability of field-programmable gate arrays.

[BibT_eX]

[DOI]

Alberto L. Sangiovanni-Vincentelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Synthesis method for field programmable gate arrays.

[BibT_eX]

[DOI]

Abbas El Gamal

Proc. IEEE, 1993

Architecture of field-programmable gate arrays.

[BibT_eX]

[DOI]

Alberto L. Sangiovanni-Vincentelli

Abbas El Gamal

Proc. IEEE, 1993

Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract).

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

A detailed router for field-programmable gate arrays.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Improving FPGA Routing Architectures Using Architecture and CAD Interactions.

[BibT_eX]

[DOI]

Benjamin Tseng

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections.

[BibT_eX]

[DOI]

Kevin Chung

Proceedings of the 29th Design Automation Conference, 1992

1991

Technology Mapping on Lookup Table-Based FPGAs for Performance.

[BibT_eX]

[DOI]

Robert J. Francis

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract).

[BibT_eX]

Proceedings of the 28th Design Automation Conference, 1991

Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs.

[BibT_eX]

[DOI]

Robert J. Francis

Proceedings of the 28th Design Automation Conference, 1991

1990

Temperature measurement and equilibrium dynamics of simulated annealing placements.

[BibT_eX]

[DOI]

Wolfgang Klebsch

Jürgen Wolf

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Parallel global routing for standard cells.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.

[BibT_eX]

[DOI]

Robert J. Francis

Kevin Chung

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988

Parallel standard cell placement algorithms with quality equivalent to simulated annealing.

[BibT_eX]

[DOI]

W. Martin Snelgrove

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

The Parallel Decomposition and Implementation of an Integrated Circuit Global Router.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGPLAN PPEALS 1988, 1988

Temperature measurement of simulated annealing placements.

[BibT_eX]

[DOI]

Wolfgang Klebsch

Jürgen Wolf

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

LocusRoute: A Parallel Global Router for Standard Cells.

[BibT_eX]

[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1985

FERMTOR: A Tunable Multiprocessor Architecture.

[BibT_eX]

[DOI]

Wayne M. Loucks