Ajay Chandna

According to our database1, Ajay Chandna authored at least 4 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation.
Proceedings of the 2024 International Symposium on Physical Design, 2024

1995
Power rail logic: a low power logic style for digital GaAs circuits.
IEEE J. Solid State Circuits, October, 1995

The Aurora RAM Compiler.
Proceedings of the 32st Conference on Design Automation, 1995

1994
An asynchronous GaAs MESFET static RAM using a new current mirror memory cell.
IEEE J. Solid State Circuits, October, 1994


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