Karem A. Sakallah

According to our database1, Karem A. Sakallah authored at least 132 papers between 1985 and 2019.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2012, "For algorithms for Boolean Satisfiability that advanced the state-of-the-art of hardware verification.".

IEEE Fellow

IEEE Fellow 1998, "For contributions to the modeling, analysis, and optimization of digital system timing.".

Timeline

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Bibliography

2019
euforia: Complete Software Model Checking with Uninterpreted Functions.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2019

I4: incremental inference of inductive invariants for verification of distributed protocols.
Proceedings of the 27th ACM Symposium on Operating Systems Principles, 2019

Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction.
Proceedings of the NASA Formal Methods - 11th International Symposium, 2019

Towards Automatic Inference of Inductive Invariants.
Proceedings of the Workshop on Hot Topics in Operating Systems, 2019

Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2014
Unbounded Scalable Verification Based on Approximate Property-Directed Reachability and Datapath Abstraction.
Proceedings of the Computer Aided Verification - 26th International Conference, 2014

2013
Detecting Traditional Packers, Decisively.
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2013

Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms.
Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

Generalized Boolean symmetries through nested partition refinement.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Conflict Anticipation in the Search for Graph Automorphisms.
Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2012

Graph Symmetry Detection and Canonical Labeling: Differences and Synergies.
Proceedings of the Turing-100, 2012

2011
Anatomy and Empirical Evaluation of Modern SAT Solvers.
Bulletin of the EATCS, 2011

Empirical Study of the Anatomy of Modern Sat Solvers.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2011, 2011

Generating Data Race Witnesses by an SMT-Based Analysis.
Proceedings of the NASA Formal Methods, 2011

Distilling critical attack graph surface iteratively through minimum-cost SAT solving.
Proceedings of the Twenty-Seventh Annual Computer Security Applications Conference, 2011

2010
Symmetry and Satisfiability: An Update.
Proceedings of the Theory and Applications of Satisfiability Testing, 2010

Trace-Driven Verification of Multithreaded Programs.
Proceedings of the Formal Methods and Software Engineering, 2010

Incorporating user control in automated interactive scheduling systems.
Proceedings of the Conference on Designing Interactive Systems, 2010

2009
Symmetry and Satisfiability.
Proceedings of the Handbook of Satisfiability, 2009

A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas.
Constraints, 2009

Dynamic symmetry-breaking for Boolean satisfiability.
Ann. Math. Artif. Intell., 2009

Generalizing Core-Guided Max-SAT.
Proceedings of the Theory and Applications of Satisfiability Testing, 2009

Dynamic Path Reduction for Software Model Checking.
Proceedings of the Integrated Formal Methods, 7th International Conference, 2009

2008
Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints.
J. Autom. Reasoning, 2008

Searching for Autarkies to Trim Unsatisfiable Clause Sets.
Proceedings of the Theory and Applications of Satisfiability Testing, 2008

Reveal: A Formal Verification Tool for Verilog Designs.
Proceedings of the Logic for Programming, 2008

Faster symmetry discovery using sparsity of symmetries.
Proceedings of the 45th Design Automation Conference, 2008

2007
Solution and Optimization of Systems of Pseudo-Boolean Constraints.
IEEE Trans. Computers, 2007

Symmetry breaking for pseudo-Boolean formulas.
ACM Journal of Experimental Algorithmics, 2007

Report on the SAT 2007 Conference on Theory and Applications of Satisfiability Testing.
AI Magazine, 2007

Improved Design Debugging Using Maximum Satisfiability.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
Efficient Symmetry Breaking for Boolean Satisfiability.
IEEE Trans. Computers, 2006

Pueblo: A Hybrid Pseudo-Boolean SAT Solver.
JSAT, 2006

Breaking Instance-Independent Symmetries In Exact Graph Coloring.
J. Artif. Intell. Res., 2006

A Progressive Simplifier for Satisfiability Modulo Theories.
Proceedings of the Theory and Applications of Satisfiability Testing, 2006

From Propositional Satisfiability to Satisfiability Modulo Theories.
Proceedings of the Theory and Applications of Satisfiability Testing, 2006

SMT(CLU): a step toward scalability in system verification.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Ario: A Linear Integer Arithmetic Logic Solver.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Refinement strategies for verification methods based on datapath abstraction.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Principles of Sequential-Equivalence Verification.
IEEE Design & Test of Computers, 2005

A Scalable Method for Solving Satisfiability of Integer Linear Arithmetic Logic.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005

A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005

On Finding All Minimally Unsatisfiable Subformulas.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Identifying Conflicts in Overconstrained Temporal Problems.
Proceedings of the IJCAI-05, Proceedings of the Nineteenth International Joint Conference on Artificial Intelligence, Edinburgh, Scotland, UK, July 30, 2005

Pueblo: A Modern Pseudo-Boolean SAT Solver.
Proceedings of the 2005 Design, 2005

A SAT-Based Decision Procedure for Mixed Logical/Integer Linear Problems.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2005

On Solving Soft Temporal Constraints Using SAT Techniques.
Proceedings of the Principles and Practice of Constraint Programming, 2005

Dynamic symmetry-breaking for improved Boolean optimization.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.
IEEE Trans. Computers, 2004

MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation.
J. UCS, 2004

AMUSE: a minimally-unsatisfiable subformula extractor.
Proceedings of the 41th Design Automation Conference, 2004

Exploiting structure in symmetry detection for CNF.
Proceedings of the 41th Design Automation Conference, 2004

Automatic abstraction and verification of verilog models.
Proceedings of the 41th Design Automation Conference, 2004

Preserving synchronizing sequences of sequential circuits after retiming.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

ShatterPB: symmetry-breaking for pseudo-Boolean formulas.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Transistor placement for noncomplementary digital VLSI cell synthesis.
ACM Trans. Design Autom. Electr. Syst., 2003

sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Satometer: how much have we searched?
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Solving difficult instances of Boolean satisfiability in the presence of symmetry.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution.
Proceedings of the Theory and Applications of Satisfiability Testing, 2003

FORCE: a fast and easy-to-implement variable-ordering heuristic.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Shatter: efficient symmetry-breaking for boolean satisfiability.
Proceedings of the 40th Design Automation Conference, 2003

SAT-based sequential depth computation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Satisfiability models and algorithms for circuit delay computation.
ACM Trans. Design Autom. Electr. Syst., 2002

A new FPGA detailed routing approach via search-based Booleansatisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Robust SAT-Based Search Algorithm for Leakage Power Reduction.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Majority-Based Decomposition of Carry Logic in Binary Adders.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Efficient Gate and Input Ordering for Circuit-to-BDD Conversion.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

ZBDD-Based Backtrack Search SAT Solver.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Resynthesis of multi-level circuits under tight constraints using symbolic optimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Generic ILP versus specialized 0-1 ILP: an update.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.
Proceedings of the Field-Programmable Logic and Applications, 2002

Search-Based SAT Using Zero-Suppressed BDDs.
Proceedings of the 2002 Design, 2002

Solving difficult SAT instances in the presence of symmetry.
Proceedings of the 39th Design Automation Conference, 2002

2001
Fast and accurate timing characterization using functionalinformation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Faster SAT and Smaller BDDs via Common Function Structure.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A boolean satisfiability-based incremental rerouting approach with application to FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

An Advanced Timing Characterization Method Using Mode Dependency.
Proceedings of the 38th Design Automation Conference, 2001

SATIRE: A New Incremental Satisfiability Engine.
Proceedings of the 38th Design Automation Conference, 2001

Scalable Hybrid Verification of Complex Microprocessors.
Proceedings of the 38th Design Automation Conference, 2001

2000
On Solving Stack-Based Incremental Satisfiability Problems.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Generalized Symmetries in Boolean Functions.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

An Experimental Study of Satisfiability Search Heuristics.
Proceedings of the 2000 Design, 2000

Constructive Library-Aware Synthesis Using Symmetries.
Proceedings of the 2000 Design, 2000

On Applying Incremental Satisfiability to Delay Fault Testing.
Proceedings of the 2000 Design, 2000

Boolean satisfiability in electronic design automation.
Proceedings of the 37th Conference on Design Automation, 2000

Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999
Timing verification of sequential dynamic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

GRASP: A Search Algorithm for Propositional Satisfiability.
IEEE Trans. Computers, 1999

Satisfiability-Based Detailed FPGA Routing.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Satisfiability-Based Functional Delay Fault Testing.
Proceedings of the VLSI: Systems on a Chip, 1999

Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Functional Timing Analysis for IP Characterization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Overview of complementary GaAs technology for high-speed VLSI circuits.
IEEE Trans. VLSI Syst., 1998

The edge-based design rule model revisited.
ACM Trans. Design Autom. Electr. Syst., 1998

AFTA: A Formal Delay Model for Functional Timing Analysis.
Proceedings of the 1998 Design, 1998

Congestion Driven Quadratic Placement.
Proceedings of the 35th Conference on Design Automation, 1998

M32: A Constructive multilevel Logic Synthesis System.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Robust Search Algorithms for Test Pattern Generation.
Proceedings of the Digest of Papers: FTCS-27, 1997

Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation.
IEEE Trans. VLSI Syst., 1996

Conflict Analysis in Search Algorithms for Satisfiability.
Proceedings of the Eigth International Conference on Tools with Artificial Intelligence, 1996

An approximate timing analysis method for datapath circuits.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

GRASP - a new search algorithm for satisfiability.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Timing verification of sequential domino circuits.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Critical paths in circuits with level-sensitive latches.
IEEE Trans. VLSI Syst., 1995

Timing models for gallium arsenide direct-coupled FET logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

The Aurora RAM Compiler.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Efficient and Robust Test Generation-Based Timing Analysis.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Macromodel Simplification Using Dimensional Analysis.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Optimization of critical paths in circuits with level-sensitive latches.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Dynamic Search-Space Pruning Techniques in Path Sensitization.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Synchronization of pipelines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

An Analysis of Path Sensitization Criteria.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Min-max linear programming and the timing analysis of digital circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Concurrent path sensitization in timing analysis.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Analysis and design of latch-controlled synchronous digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Ravel: assigned-delay compiled-code logic simulation.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Using constraint geometry to determine maximum rate pipeline clocking.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Identification of critical paths in circuits with level-sensitive latches.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Delay macromodels for the timing analysis of GaAs DCFL.
Proceedings of the conference on European design automation, 1992

1991
The Design of a Microsupercomputer.
IEEE Computer, 1991

Optimal Clocking of Circular Pipelines.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

FPD - An Environment for Exact Timing Analysis.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
A first-order charge conserving MOS capacitance model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-section Clock Derivation.
Proceedings of the First International Conference on Systems Integration, 1990

check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1985
SAMSON2: An Event Driven VLSI Circuit Simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985


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