Karem A. Sakallah
Orcid: 0000000258199089Affiliations:
 University of Michigan, Ann Arbor, USA
According to our database^{1},
Karem A. Sakallah
authored at least 142 papers
between 1985 and 2023.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2012, "For algorithms for Boolean Satisfiability that advanced the stateoftheart of hardware verification.".
IEEE Fellow
IEEE Fellow 1998, "For contributions to the modeling, analysis, and optimization of digital system timing.".
Timeline
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Bibliography
2023
Innov. Syst. Softw. Eng., December, 2023
Proceedings of the Formal Techniques for Distributed Objects, Components, and Systems, 2023
SATBased Quantified Symmetric Minimization of the Reachable States of Distributed Protocols.
Proceedings of the Formal Methods in ComputerAided Design, 2023
2021
Proceedings of the Handbook of Satisfiability  Second Edition, 2021
Proceedings of the 19th International Workshop on Satisfiability Modulo Theories colocated with 33rd International Conference on Computer Aided Verification(CAV 2021), 2021
Proceedings of the NASA Formal Methods  13th International Symposium, 2021
Proceedings of the Formal Methods in Computer Aided Design, 2021
2020
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2020
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020
2019
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2019
I4: incremental inference of inductive invariants for verification of distributed protocols.
Proceedings of the 27th ACM Symposium on Operating Systems Principles, 2019
Proceedings of the NASA Formal Methods  11th International Symposium, 2019
Proceedings of the Workshop on Hot Topics in Operating Systems, 2019
Empirical Evaluation of IC3Based Model Checking Techniques on Verilog RTL Designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2014
Unbounded Scalable Verification Based on Approximate PropertyDirected Reachability and Datapath Abstraction.
Proceedings of the Computer Aided Verification  26th International Conference, 2014
2013
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2013
Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2013
2012
Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2012
Proceedings of the Turing100, 2012
2011
Bull. EATCS, 2011
Proceedings of the Theory and Applications of Satisfiability Testing  SAT 2011, 2011
Proceedings of the NASA Formal Methods, 2011
Distilling critical attack graph surface iteratively through minimumcost SAT solving.
Proceedings of the TwentySeventh Annual Computer Security Applications Conference, 2011
2010
Proceedings of the Theory and Applications of Satisfiability Testing, 2010
Proceedings of the Formal Methods and Software Engineering, 2010
Proceedings of the Conference on Designing Interactive Systems, 2010
2009
Proceedings of the Handbook of Satisfiability, 2009
A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas.
Constraints An Int. J., 2009
Ann. Math. Artif. Intell., 2009
Proceedings of the Theory and Applications of Satisfiability Testing, 2009
Proceedings of the Integrated Formal Methods, 7th International Conference, 2009
2008
J. Autom. Reason., 2008
Proceedings of the Theory and Applications of Satisfiability Testing, 2008
Proceedings of the Logic for Programming, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
IEEE Trans. Computers, 2007
ACM J. Exp. Algorithmics, 2007
Report on the SAT 2007 Conference on Theory and Applications of Satisfiability Testing.
AI Mag., 2007
Proceedings of the Formal Methods in ComputerAided Design, 7th International Conference, 2007
2006
IEEE Trans. Computers, 2006
J. Satisf. Boolean Model. Comput., 2006
J. Artif. Intell. Res., 2006
Proceedings of the Theory and Applications of Satisfiability Testing, 2006
Proceedings of the Theory and Applications of Satisfiability Testing, 2006
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the Formal Methods in ComputerAided Design, 6th International Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASPDAC 2006, 2006
2005
IEEE Des. Test Comput., 2005
Proceedings of the Theory and Applications of Satisfiability Testing, 2005
A BranchandBound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas.
Proceedings of the Theory and Applications of Satisfiability Testing, 2005
Proceedings of the Theory and Applications of Satisfiability Testing, 2005
Proceedings of the IJCAI05, Proceedings of the Nineteenth International Joint Conference on Artificial Intelligence, Edinburgh, Scotland, UK, July 30, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2005
Proceedings of the Principles and Practice of Constraint Programming, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.
IEEE Trans. Computers, 2004
MINCE: A Static Global VariableOrdering Heuristic for SAT Search and BDD Manipulation.
J. Univers. Comput. Sci., 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
ACM Trans. Design Autom. Electr. Syst., 2003
subSAT: a formulation for relaxed Boolean satisfiability with applications in routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Solving difficult instances of Boolean satisfiability in the presence of symmetry.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution.
Proceedings of the Theory and Applications of Satisfiability Testing, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
MajorityBased Decomposition of Carry Logic in Binary Adders.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Efficient Gate and Input Ordering for CircuittoBDD Conversion.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
ZBDDBased Backtrack Search SAT Solver.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Resynthesis of multilevel circuits under tight constraints using symbolic optimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computeraided Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computeraided Design, 2002
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.
Proceedings of the FieldProgrammable Logic and Applications, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2001 IEEE/ACM International Conference on ComputerAided Design, 2001
A boolean satisfiabilitybased incremental rerouting approach with application to FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 38th Design Automation Conference, 2001
2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE/ACM International Conference on ComputerAided Design, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Computers, 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Transistor level microplacement and routing for twodimensional digital VLSI cell synthesis.
Proceedings of the 1999 International Symposium on Physical Design, 1999
SatisfiabilityBased Functional Delay Fault Testing.
Proceedings of the VLSI: Systems on a Chip, 1999
SatisfiabilityBased Layout Revisited: Detailed Routing of Complex FPGAs vis SearchBased Boolean SAT.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
ACM Trans. Design Autom. Electr. Syst., 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
Proceedings of the Digest of Papers: FTCS27, 1997
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1996
RavelXL: a hardware accelerator for assigneddelay compiledcode logic gate simulation.
IEEE Trans. Very Large Scale Integr. Syst., 1996
Proceedings of the Eigth International Conference on Tools with Artificial Intelligence, 1996
Proceedings of the 1996 IEEE/ACM International Conference on ComputerAided Design, 1996
Proceedings of the 1996 IEEE/ACM International Conference on ComputerAided Design, 1996
Proceedings of the 1996 IEEE/ACM International Conference on ComputerAided Design, 1996
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time.
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Maximum rate singlephase clocking of a closed pipeline including wave pipelining, stoppability, and startability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 32st Conference on Design Automation, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE/ACM International Conference on ComputerAided Design, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 1993 IEEE/ACM International Conference on ComputerAided Design, 1993
Proceedings of the European Design Automation Conference 1993, 1993
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
Proceedings of the 1992 IEEE/ACM International Conference on ComputerAided Design, 1992
Proceedings of the 1992 IEEE/ACM International Conference on ComputerAided Design, 1992
Proceedings of the 1992 IEEE/ACM International Conference on ComputerAided Design, 1992
Proceedings of the conference on European design automation, 1992
1991
Computer, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the 1991 IEEE/ACM International Conference on ComputerAided Design, 1991
1990
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and Onsection Clock Derivation.
Proceedings of the First International Conference on Systems Integration, 1990
<i>check</i> T<sub>c</sub> and <i>min</i> T<sub>c</sub>: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits.
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 1990
1985
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985