Haoxing Ren

According to our database1, Haoxing Ren authored at least 40 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.
CoRR, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.
CoRR, 2021

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accelerating Chip Design With Machine Learning.
IEEE Micro, 2020

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.
CoRR, 2020

ML for CAD - Where is the Treasure Hiding?
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Toward Intelligent Physical Design: Deep Learning and GPU Acceleration.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

PRIMAL: Power Inference using Machine Learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
RouteNet: routability prediction for mixed-size designs using convolutional neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018

2014
A brief introduction on contemporary High-Level Synthesis.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
Network flow based datapath bit slicing.
Proceedings of the International Symposium on Physical Design, 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Intuitive ECO synthesis for high performance circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev., 2011

2010
Logical and physical restructuring of fan-in trees.
Proceedings of the 2010 International Symposium on Physical Design, 2010

History-based VLSI legalization using network flow.
Proceedings of the 47th Design Automation Conference, 2010

2009
Low cost test point insertion without using extra registers for high performance design.
Proceedings of the 2009 IEEE International Test Conference, 2009

DeltaSyn: An efficient logic difference optimizer for ECO synthesis.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Timing-Driven Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Placement-Driven Synthesis Design Closure Tool.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2007
Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
Sensitivity guided net weighting for placement-driven synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Computational geometry based placement migration.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Diffusion-based placement migration.
Proceedings of the 42nd Design Automation Conference, 2005

2004
True crosstalk aware incremental placement with noise map.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004


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