Chia-Tung Ho

According to our database, Chia-Tung Ho authored at least 13 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation.

Chia-Tung Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Haoxing Ren

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.

Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.

Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin

IEEE Trans. Very Large Scale Integr. Syst., 2022

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.

Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin

IEEE Access, 2022

Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization.

Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.

Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park

IEEE Trans. Very Large Scale Integr. Syst., 2021

SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.

Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning.

Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

2020

A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT.

Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop.

Chia-Tung Ho, Andrew B. Kahng

Proceedings of the International Conference on Computer-Aided Design, 2019

2017

InTraSim: Incremental Transient Simulation of Power Grids.

Yu-Min Lee, Chia-Tung Ho

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2014

Incremental transient simulation of power grid.

Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng

Proceedings of the International Symposium on Physical Design, 2014

2013

Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.

Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013