Akihiro Chiyonobu

According to our database, Akihiro Chiyonobu authored at least 10 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

A Low-Power Instruction Issue Queue for Microprocessors.

Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato

IEICE Trans. Electron., 2008

2007

Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism.

Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu

Int. J. Comput. Their Appl., 2007

Challenges in Evaluations for a Typical-Case Design Methodology.

Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Indirect Tag Search Mechanism for Instruction Window Energy Reduction.

Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato

Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006

Energy-efficient instruction scheduling utilizing cache miss information.

Akihiro Chiyonobu, Toshinori Sato

SIGARCH Comput. Archit. News, 2006

A leakage-energy-reduction technique for cache memories in embedded processors.

Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato

J. Embed. Comput., 2006

Evaluating the Impact of Fault Recovery on Superscalar Processor Performance.

Toshinori Sato, Akihiro Chiyonobu

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors.

Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

An Energy-Efficient Clustered Superscalar Processor.

Toshinori Sato, Akihiro Chiyonobu

IEICE Trans. Electron., 2005

2004

Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.

Akihiro Chiyonobu, Toshinori Sato

Proceedings of the Intenational Symposium on Information and Communication Technologies, 2004