Toshinori Sato

According to our database, Toshinori Sato authored at least 107 papers between 1997 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Building a hospitable and reliable dialogue system for android robots: a scenario-based approach with large language models.

Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Tomoya Mizumoto, Masaya Ohagi, Toshinori Sato

Adv. Robotics, November, 2023

PHALM: Building a Knowledge Graph from Scratch by Prompting Humans and a Language Model.

Tatsuya Ide, Eiki Murata, Daisuke Kawahara, Takato Yamazaki, Shengzhe Li, Kenta Shinzato, Toshinori Sato

CoRR, 2023

Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks? - Investigation of the Effects of Question Marks on Dialogue Systems.

Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato

CoRR, 2023

An Open-Domain Avatar Chatbot by Exploiting a Large Language Model.

Takato Yamazaki, Tomoya Mizumoto, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato

Proceedings of the 24th Meeting of the Special Interest Group on Discourse and Dialogue, 2023

Bridging the Gap between Subword and Character Segmentation in Pretrained Language Models.

Shun Kiyono, Sho Takase, Shengzhe Li, Toshinori Sato

Proceedings of the 14th International Conference on Recent Advances in Natural Language Processing, 2023

A Follow-up Study on Evaluation Metrics Using Follow-up Utterances.

Toshiki Kawamoto, Yuki Okano, Takato Yamazaki, Toshinori Sato, Kotaro Funakoshi, Manabu Okumura

Proceedings of the 37th Pacific Asia Conference on Language, 2023

Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition.

Toshinori Sato, Hiroyuki Hama, Tomoaki Ukezono

Proceedings of the 20th International SoC Design Conference, 2023

Leveraging Approximate Computing for IoT Image Transmission.

Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 20th International SoC Design Conference, 2023

Negative Impact of Approximated Signed Addition on Power Reduction.

Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato

Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

Towards At-the-Edge ECG Signal Processing with Accuracy-tunable Approximate Adders.

Hiroyuki Hama, Toshinori Sato

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022

Tourist Guidance Robot Based on HyperCLOVA.

Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Masaya Ohagi, Tomoya Mizumoto, Shuta Ichimura, Yusuke Kida, Toshinori Sato

CoRR, 2022

Building a Personalized Dialogue System with Prompt-Tuning.

Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato

Proceedings of the 2022 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies: Student Research Workshop, 2022

Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Accuracy-Controllable Approximate Adder for FPGAs.

Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), 2022

2020

Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations.

Toshinori Sato, Tomoaki Ukezono

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

An Accuracy-Configurable Adder for Low-Power Applications.

Tongxin Yang, Toshinori Sato, Tomoaki Ukezono

IEICE Trans. Electron., 2020

A Dynamically Configurable Approximate Array Multiplier with Exact Mode.

Toshinori Sato, Tomoaki Ukezono

Proceedings of the 5th International Conference on Computer and Communication Systems, 2020

2019

Design and Analysis of Approximate Multipliers with a Tree Compressor.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Trading Accuracy for Power with a Configurable Approximate Adder.

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono

IEICE Trans. Electron., 2019

Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance.

Toshinori Sato, Tomoaki Ukezono

Proceedings of the 24th IEEE Pacific Rim International Symposium on Dependable Computing, 2019

On Applications of Configurable Approximation to Irregular Voltage.

Toshinori Sato, Tomoaki Ukezono

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area.

Tongxin Yang, Toshinori Sato, Tomoaki Ukezono

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Low-Power Approximate Multiply-Add Unit.

Tongxin Yang, Toshinori Sato, Tomoaki Ukezono

Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Tolerating Aging-Induced Timing Violations Via Configurable Approximations.

Toshinori Sato, Tomoaki Ukezono

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Correcting Sign Calculation Errors in Configurable Approximations.

Toshinori Sato, Tomoaki Ukezono

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing.

Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A low-power configurable adder for approximate applications.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Exploiting Configurability for Correct Sign Calculation in an Approximate Adder.

Toshinori Sato, Tomoaki Ukezono

Proceedings of the International SoC Design Conference, 2018

Approximate Adder Generation for Image Processing Using Convolutional Neural Network.

Ryuta Ishida, Toshinori Sato, Tomoaki Ukezono

Proceedings of the International SoC Design Conference, 2018

A Low-Power Yet High-Speed Configurable Adder for Approximate Computing.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A low-power high-speed accuracy-controllable approximate multiplier design.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor.

Tongxin Yang, Tomoaki Ukezono, Toshinori Sato

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2013

Improving timing error tolerance without impact on chip area and power consumption.

Ken Yano, Takanori Hayashida, Toshinori Sato

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

A Selective Replacement Method for Timing-Error-Predicting flip-Flops.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

J. Circuits Syst. Comput., 2012

Analysis of SER Improvement by Radiation Hardened Latches.

Ken Yano, Takanori Hayashida, Toshinori Sato

Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

Guidelines for mitigating NBTI degradation in on-chip memories.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

Proceedings of the International Symposium on Communications and Information Technologies, 2012

Dynamically reducing overestimated design margin of MultiCores.

Toshinori Sato, Takanori Hayashida, Ken Yano

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Topic 4: High-Performance Architecture and Compilers.

Alex Veidenbaum, Nectarios Koziris, Toshinori Sato, Avi Mendelson

Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Importance of Single-Core Performance in the Multicore Era.

Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida

Proceedings of the Thirty-Fifth Australasian Computer Science Conference, 2012

2011

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

IEICE Trans. Electron., 2011

Multicore Power Management Utilizing Error-Predicting Flip-flop.

Toshinori Sato, Takahito Yoshiki, Takanori Hayashida

Proceedings of the International Conference on Complex, 2011

2010

A Replacement Strategy for Canary Flip-Flops.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Signal probability control for relieving NBTI in SRAM cells.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment.

Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura

IEICE Trans. Electron., 2009

A case for exploiting complex arithmetic circuits towards performance yield enhancement.

Shingo Watanabe, Masanori Hashimoto, Toshinori Sato

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Uncriticality-directed scheduling for tackling variation and power challenges.

Toshinori Sato, Shingo Watanabe

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

A Low-Power Instruction Issue Queue for Microprocessors.

Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato

IEICE Trans. Electron., 2008

A Simple Mechanism for Collapsing Instructions under Timing Speculation.

Toshinori Sato

IEICE Trans. Electron., 2008

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications.

Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Uncriticality-Directed Low-Power Instruction Scheduling.

Shingo Watanabe, Toshinori Sato

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Instruction Scheduling for Variation-Originated Variable Latencies.

Toshinori Sato, Shingo Watanabe

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Formulating MITF for a Multicore Processor with SEU Tolerance.

Toshimasa Funaki, Toshinori Sato

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Dependability, power, and performance trade-off on a multicore processor.

Toshinori Sato, Toshimasa Funaki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Introduction.

Kenji Kise, Toshinori Sato, Hironori Nakajo

SIGARCH Comput. Archit. News, 2007

Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism.

Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu

Int. J. Comput. Their Appl., 2007

Power-Performance Trade-Off of a Dependable Multicore Processor.

Toshinori Sato, Toshimasa Funaki

Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

Exploiting Input Variations for Energy Reduction.

Toshinori Sato, Yuji Kunitake

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM.

Toshinori Sato, Yuji Kunitake

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Challenges in Evaluations for a Typical-Case Design Methodology.

Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Indirect Tag Search Mechanism for Instruction Window Energy Reduction.

Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato

Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006

Energy-efficient instruction scheduling utilizing cache miss information.

Akihiro Chiyonobu, Toshinori Sato

SIGARCH Comput. Archit. News, 2006

A leakage-energy-reduction technique for cache memories in embedded processors.

Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato

J. Embed. Comput., 2006

Evaluating the Impact of Fault Recovery on Superscalar Processor Performance.

Toshinori Sato, Akihiro Chiyonobu

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors.

Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

An Energy-Efficient Clustered Superscalar Processor.

Toshinori Sato, Akihiro Chiyonobu

IEICE Trans. Electron., 2005

Profiling with Helper Threads.

Takamasa Tokunaga, Toshinori Sato

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Folding Active List for High Performance and Low Power.

Yuichiro Imaizumi, Toshinori Sato

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Exploiting Trivial Computation in Dependable Processors.

Toshinori Sato

Proceedings of the 20th International Conference on Computers and Their Applications, 2005

2004

A leakage-energy-reduction technique for highly-associative caches in embedded systems.

Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato

SIGARCH Comput. Archit. News, 2004

The potential in energy efficiency of a speculative chip-multiprocessor.

Yuu Tanaka, Toshinori Sato, Takenori Koushiro

Proceedings of the SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2004

Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.

Akihiro Chiyonobu, Toshinori Sato

Proceedings of the Intenational Symposium on Information and Communication Technologies, 2004

Leakage Energy Reduction in Register Renaming.

Masaharu Goto, Toshinori Sato

Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.

Seiichiro Fujii, Toshinori Sato

Proceedings of the Embedded and Ubiquitous Computing, 2004

A static and dynamic energy reduction technique for I-cache and BTB in embedded processors.

Hidenori Sato, Toshinori Sato

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A trace-level value predictor for Contrail processors.

Takenori Koushiro, Toshinori Sato, Itsujiro Arita

SIGARCH Comput. Archit. News, 2003

Combining variable latency pipeline with instruction reuse for execution latency reduction.

Toshinori Sato, Itsujiro Arita

Syst. Comput. Jpn., 2003

Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction.

Akihito Sakanaka, Toshinori Sato

Proceedings of the Integrated Circuit and System Design, 2003

A field-customizable and runtime-adaptable microarchitecture.

Toshinori Sato, Daisuke Morishita

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Exploiting Instruction Redundancy for Transient Fault Tolerance.

Toshinori Sato

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation.

Asami Tanino, Toshinori Sato

Proceedings of the 16th International Conference on Computer Applications in Industry and Engineering, 2003

2002

Evaluating the impact of reissued instructions on data speculative processor performance.

Toshinori Sato

Microprocess. Microsystems, 2002

Evaluating Influence of Compiler Optimizations on Data Speculation.

Toshinori Sato, Kiichi Sugitani, Akihiko Hamano

J. Inf. Sci. Eng., 2002

The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization.

Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Reducing Energy Consumption via Low-Cost Value Prediction.

Toshinori Sato, Itsujiro Arita

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Low-Cost Value Predictors Using Frequent Value Locality.

Toshinori Sato, Itsujiro Arita

Proceedings of the High Performance Computing, 4th International Symposium, 2002

Simplifying Instruction Issue Logic in Superscalar Processors.

Toshinori Sato, Itsujiro Arita

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications.

Toshinori Sato, Itsujiro Arita

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

In Search of Efficient Reliable Processor Design.

Toshinori Sato, Itsujiro Arita

Proceedings of the 2001 International Conference on Parallel Processing, 2001

Influence of Compiler Optimizations on Value Prediction.

Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita

Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001

Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse.

Toshinori Sato, Itsujiro Arita

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Tolerating Transient Faults through an Instruction Reissue Mechanism.

Toshinori Sato, Itsujiro Arita

Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001

2000

Vector Unit Architecture for Emotion Synthesis.

Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki

IEEE Micro, 2000

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.

Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki

IEEE J. Solid State Circuits, 2000

Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism.

Toshinori Sato

J. Syst. Archit., 2000

The KIT COSMOS Processor: Introducing CONDOR.

Toshinori Sato, Itsujiro Arita

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Comprehensive Evaluation of an Instruction Reissue Mechanism.

Toshinori Sato, Itsujiro Arita

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Table size reduction for data value predictors by exploiting narrow width values.

Toshinori Sato, Itsujiro Arita

Proceedings of the 14th international conference on Supercomputing, 2000

Partial Resolution in Data Value Predictors.

Toshinori Sato, Itsujiro Arita

Proceedings of the 2000 International Conference on Parallel Processing, 2000

300MHz design methodology of VU for emotion synthesis.

Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu

Proceedings of ASP-DAC 2000, 2000

1999

A Simulation Study of Combining Load Value and Address Predictors.

Toshinori Sato

Int. J. High Speed Comput., 1999

Profile-Based Selection of Load Value and Address Predictors.

Toshinori Sato

Proceedings of the High Performance Computing, Second International Symposium, 1999

Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure.

Toshinori Sato

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism.

Toshinori Sato

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998

Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue.

Toshinori Sato

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

Data Dependence Path Reductio with Tunneling Load Instructions.

Toshinori Sato

Proceedings of the High Performance Computing, International Symposium, 1997