Alessio Di Pasquo

According to our database, Alessio Di Pasquo authored at least 4 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz.

Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi

IEEE J. Solid State Circuits, April, 2025

2024

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.

Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2021

A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC.

Alessio Di Pasquo, Claudio Nani, Enrico Monaco, Luca Fanucci

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Delay-lines jitter modeling and efficiency analysis in FinFET technology.

Alessio Di Pasquo, Enrico Monaco, Claudio Nani, Luca Fanucci

Proceedings of the 28th IEEE International Conference on Electronics, 2021