Enrico Temporiti
According to our database1,
Enrico Temporiti
authored at least 24 papers
between 2003 and 2019.
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Bibliography
2019
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS.
IEEE J. Solid State Circuits, 2019
A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2016
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures.
IEEE J. Solid State Circuits, 2016
23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Power consumption estimation for the silicon-photonics reflective ONU conceived within the FABULOUS European project.
Proceedings of the 17th International Conference on Transparent Optical Networks, 2015
2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 16th International Conference on Transparent Optical Networks, 2014
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.
Proceedings of the ESSCIRC 2014, 2014
A 5<sup>th</sup> order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS.
Proceedings of the ESSCIRC 2014, 2014
2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE J. Solid State Circuits, 2011
2010
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
IEEE J. Solid State Circuits, 2010
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2004
A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications.
IEEE J. Solid State Circuits, 2004
2003
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003