Claudio Nani
Orcid: 0000-0003-1095-8506
According to our database1,
Claudio Nani
authored at least 15 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2021
A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
2020
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2020
2019
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2016
A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
2011
A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters.
IEICE Trans. Electron., 2009
2008
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications.
Proceedings of the Design, Automation and Test in Europe, 2008