Alexander S. Kamkin

Orcid: 0000-0001-6374-8575

Affiliations:
  • Russian Academy of Sciences, Institute for System Programming, Moscow, Russia


According to our database1, Alexander S. Kamkin authored at least 24 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
High-Level Synthesis versus Hardware Construction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2020
Deductive Binary Code Verification Against Source-Code-Level Specifications.
Proceedings of the Tests and Proofs - 14th International Conference, 2020

2019
Open-Source Validation Suite for RISC-V.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

2018
Test Program Generator MicroTESK for RISC-V.
Proceedings of the 19th International Workshop on Microprocessor and SOC Test and Verification, 2018

2017
Maintaining ISA Specifications in MicroTESK Test Program Generator.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

MicroTESK: Specification-Based Tool for Constructing Test Program Generators.
Proceedings of the Hardware and Software: Verification and Testing, 2017

MicroTESK: A Tool for Constrained Random Test Program Generation for Microprocessors.
Proceedings of the Perspectives of System Informatics, 2017

2016
Testing logic circuits at different abstraction levels: An experimental evaluation.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

An EFSM-driven and model checking-based approach to functional test generation for hardware designs.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Universal mitigation of NBTI-induced aging by design randomization.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

ESL design with RTL-verified predesigned abstract communication channels.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Applying parameterized model checking to real-life cache coherence protocols.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Projecting transition systems: Overcoming state explosion in concurrent system verification.
Program. Comput. Softw., 2015

Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

2014
Extensible environment for test program generation for microprocessors.
Program. Comput. Softw., 2014

2013
Runtime Verification Based on Executable Models: On-the-Fly Matching of Timed Traces
Proceedings of the Proceedings Eighth Workshop on Model-Based Testing, 2013

Static analysis of HDL descriptions: Extracting models for verification.
Proceedings of the East-West Design & Test Symposium, 2013

2011
Survey of modern technologies of simulation-based verification of hardware.
Program. Comput. Softw., 2011

A TLM-based approach to functional verification of hardware components at different abstraction levels.
Proceedings of the 12th Latin American Test Workshop, 2011

Reconfigurable Model-Based Test Program Generator for Microprocessors.
Proceedings of the Fourth IEEE International Conference on Software Testing, 2011

Simulation-based hardware verification with time-abstract models.
Proceedings of the 9th East-West Design & Test Symposium, 2011

2008
Coverage-directed verification of microprocessor units based on cycle-accurate contract specifications.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

2007
The use of contract specifications for representing requirements and for functional testing of hardware models.
Program. Comput. Softw., 2007

2006
The UniTESK Approach to Specification-Based Validation of Hardware Designs.
Proceedings of the Leveraging Applications of Formal Methods, 2006


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