Maksim Jenihhin

According to our database, Maksim Jenihhin authored at least 112 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks.

Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin

ACM Comput. Surv., June, 2024

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators.

Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio

CoRR, 2024

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators.

Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin

CoRR, 2024

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators.

Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik

CoRR, 2024

Structural Decision Diagrams in Digital Test - Theory and Applications

Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman

Springer, ISBN: 978-3-031-44733-4, 2024

2023

An automated method for mining high-quality assertion sets.

Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri

Microprocess. Microsystems, March, 2023

Unsupervised Recycled FPGA Detection Using Symmetry Analysis.

Tanvir Ahmad Tarique, Foisal Ahmed, Maksim Jenihhin, Liakot Ali

CoRR, 2023

Applying RIS-Based Communication for Collaborative Computing in a Swarm of Drones.

Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin

IEEE Access, 2023

Special Session: Approximation and Fault Resiliency of DNN Accelerators.

Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Analyzing Side-Channel Attack Vulnerabilities at RTL.

Xinhui Lai, Maksim Jenihhin

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Holistic IJTAG-based External and Internal Fault Monitoring in UAVs.

Foisal Ahmed, Maksim Jenihhin

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators.

Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

ML-Based Online Design Error Localization for RISC-V Implementations.

Hardi Selg, Maksim Jenihhin, Peeter Ellervee, Jaan Raik

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment.

Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin

Proceedings of the IEEE European Test Symposium, 2023

On-Chip Sensors Data Collection and Analysis for SoC Health Management.

Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors.

Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

Enhancing Fault Resilience of QNNs by Selective Neuron Splitting.

Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

A Survey on UAV Computing Platforms: A Hardware Reliability Perspective.

Foisal Ahmed, Maksim Jenihhin

Sensors, 2022

On BTI Aging Rejuvenation in Memory Address Decoders.

Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test.

Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A Novel Fault-Tolerant Logic Style with Self-Checking Capability.

Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani, Maksim Jenihhin

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors.

Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

2021

Fast and Fair Computation Offloading Management in a Swarm of Drones Using a Rating-Based Federated Learning Approach.

Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin

IEEE Access, 2021

On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines.

Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

A Methodology for Automated Mining of Compact and Accurate Assertion Sets.

Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Edge-to-Fog Collaborative Computing in a Swarm of Drones.

Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin

Proceedings of the Advances in Model and Data Engineering in the Digitalization Era, 2021

Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis.

Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules.

Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

JÄNES: A NAS Framework for ML-based EDA Applications.

Hardi Selg, Maksim Jenihhin, Peeter Ellervee

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Modeling Soft-Error Reliability Under Variability.

Aneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs.

Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik

Microprocess. Microsystems, 2020

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik

J. Electron. Test., 2020

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks.

Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices.

Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects.

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Wafer-Level Die Re-Test Success Prediction Using Machine Learning.

Hardi Selg, Maksim Jenihhin, Peeter Ellervee

Proceedings of the IEEE Latin-American Test Symposium, 2020

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL.

Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.

Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.

Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Understanding multidimensional verification: Where functional meets non-functional.

Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu

Microprocess. Microsystems, 2019

High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik

CoRR, 2019

An optimization framework for dynamic pipeline management in computing systems.

Syed Rameez Naqvi, Anjum Zahid, Lina Sawalha, Syed Saud Naqvi, Tallha Akram, Sajjad Ali Haider, Kumar Yelamarthi, Maksim Jenihhin

Comput. Electr. Eng., 2019

On Test Generation for Microprocessors for Extended Class of Functional Faults.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Implementation-Independent Functional Test Generation for MSC Microprocessors.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks.

Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications.

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing.

Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Mixed-level identification of fault redundancy in microprocessors.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik

Proceedings of the IEEE Latin American Test Symposium, 2019

Software-Based Mitigation for Memory Address Decoder Aging.

Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui

Proceedings of the IEEE Latin American Test Symposium, 2019

PASCAL: Timing SCA Resistant Design and Verification Flow.

Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Application Specific True Critical Paths Identification in Sequential Circuits.

Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Efficient Fault Injection based on Dynamic HDL Slicing Technique.

Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.

Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors.

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik

Proceedings of the 24th IEEE European Test Symposium, 2019

True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits.

Raimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Challenges of Reliability Assessment and Enhancement in Autonomous Systems.

Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

New categories of Safe Faults in a processor-based Embedded System.

Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors.

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019

2018

Fast identification of true critical paths in sequential circuits.

Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi

Microelectron. Reliab., 2018

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.

Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits.

Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Towards Multidimensional Verification: Where Functional Meets Non-Functional.

Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Timing-critical path analysis with structurally synthesized BDDs.

Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies

Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality.

Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda

Proceedings of the 12th European Workshop on Microelectronics Education, 2018

Software-Level TMR Approach for On-Board Data Processing in Space Applications.

Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.

Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017

Multi-Fragment Markov Model Guided Online Test Generation for MPSoC.

Jüri Vain, Leonidas Tsiopoulos, Vyacheslav S. Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik

Proceedings of the 13th International Conference on ICT in Education, 2017

A scalable technique to identify true critical paths in sequential circuits.

Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

BASTION: Board and SoC test instrumentation for ageing and no failure found.

Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits.

Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros

J. Electron. Test., 2016

Gate-level modelling of NBTI-induced delays under process variations.

Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar

Proceedings of the 17th Latin-American Test Symposium, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.

Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Universal mitigation of NBTI-induced aging by design randomization.

Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs.

Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG.

N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls

Proceedings of the 16th Latin-American Test Symposium, 2015

FSMD RTL design manipulation for clock interface abstraction.

Syed Saif Abrar, Maksim Jenihhin, Jaan Raik

Proceedings of the 2015 International Conference on Advances in Computing, 2015

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.

Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores.

Syed Saif Abrar, Maksim Jenihhin, Jaan Raik

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Automated Design Error Localization in RTL Designs.

Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke

IEEE Des. Test, 2014

Hierarchical identification of NBTI-critical gates in nanoscale logic.

Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti

Proceedings of the 15th Latin American Test Workshop, 2014

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation.

Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar

Proceedings of the Applications of Evolutionary Computation - 17th European Conference, 2014

2013

Automated design error debug using high-level decision diagrams and mutation operators.

Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin

Microprocess. Microsystems, 2013

Assessment of diagnostic test for automated bug localization.

Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar

Proceedings of the 14th Latin American Test Workshop, 2013

Performance analysis of cosimulating processor core in VHDL and SystemC.

Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu

Proceedings of the International Conference on Advances in Computing, 2013

Identifying NBTI-Critical Paths in Nanoscale Logic.

Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Extensible open-source framework for translating RTL VHDL IP cores to SystemC.

Syed Saif Abrar, Maksim Jenihhin, Jaan Raik

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.

Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara

J. Electron. Test., 2012

On the Reuse of TLM Mutation Analysis at RTL.

Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar

J. Electron. Test., 2012

A scalable model based RTL framework zamiaCAD for static analysis.

Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Localization of Bugs in Processor Designs Using zamiaCAD Framework.

Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

PSL assertion checkers synthesis with ASM based HLS tool ABELITE.

Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov

Proceedings of the 13th Latin American Test Workshop, 2012

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis.

Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar

Proceedings of the 13th Latin American Test Workshop, 2012

Combining dynamic slicing and mutation operators for ESL correction.

Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Mutation analysis for SystemC designs at TLM.

Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar

Proceedings of the 12th Latin American Test Workshop, 2011

EEG Analyzer prototype based on FPGA.

Maksim Jenihhin, Maksim Gorev, Vadim Pesonen, Dmitri Mihhailov, Peeter Ellervee, Hiie Hinrikus, Maie Bachmann, Jaanus Lass

Proceedings of the 7th International Symposium on Image and Signal Processing and Analysis, 2011

Automated test bench generation for high-level synthesis flow ABELITE.

Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov

Proceedings of the 9th East-West Design & Test Symposium, 2011

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.

Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara

Proceedings of the 16th European Test Symposium, 2011

2010

Mutation analysis with high-level decision diagrams.

Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi

Proceedings of the 11th Latin American Test Workshop, 2010

An approach for PSL assertion coverage analysis with high-level decision diagrams.

Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Constraint-based test pattern generation at the Register-Transfer Level.

Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams.

Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar

J. Electron. Test., 2009

High-Level Decision Diagrams based coverage metrics for verification and test.

Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar

Proceedings of the 10th Latin American Test Workshop, 2009

2008

Mixed hierarchical-functional fault models for targeting sequential cores.

Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin

J. Syst. Archit., 2008

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation.

Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar

Proceedings of the 13th European Test Symposium, 2008

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.

Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.

Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Code Coverage Analysis using High-Level Decision Diagrams.

Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Layout to Logic Defect Analysis for Hierarchical Test Generation.

Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Test Time Minimization for Hybrid BIST of Core-Based Systems.

Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin

J. Comput. Sci. Technol., 2006

2004

Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting.

Raimund Ubar, Maksim Jenihhin

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture.

Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003