Georgi Gaydadjiev

According to our database1, Georgi Gaydadjiev authored at least 155 papers between 1996 and 2019.

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Bibliography

2019
Memory Mapping for Multi-die FPGAs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
The Case for Polymorphic Registers in Dataflow Computing.
International Journal of Parallel Programming, 2018

EXA2PRO programming environment: architecture and applications.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018



2017
AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

RAW Keynote Speakers.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Convolutional Neural Networks on Dataflow Engines.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Cloud Deployment and Management of Dataflow Engines.
Proceedings of the 1st International Workshop on Next generation of Cloud Architectures, 2017

From exaflop to exaflow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Rapid Development of Gzip with MaxJ.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Construction and Evaluation of an Ultra Low Latency Frameless Renderer for VR.
IEEE Trans. Vis. Comput. Graph., 2016

An AppGallery for dataflow computing.
J. Big Data, 2016

Automated dataflow graph merging.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Online evolving fuzzy rule-based prediction model for high frequency trading financial data stream.
Proceedings of the 2016 IEEE Conference on Evolving and Adaptive Intelligent Systems, 2016


The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

Spatial Programming with OpenSPL.
Proceedings of the FPGAs for Software Programmers, 2016

2015
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Bit-Flip Aware Control-Flow Error Detection.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Ultra low latency dataflow renderer.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Low-Cost Software Control-Flow Error Recovery.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A non-conservative software-based approach for detecting illegal CFEs caused by transient faults.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014
Towards scalable arithmetic units with graceful degradation.
ACM Trans. Embedded Comput. Syst., 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

Towards domain-specific Instruction-Set Generation.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

EUROSERVER: Energy Efficient Node for European Micro-Servers.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Towards Code Safety with High Performance.
Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014


Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Custom architecture for multicore audio beamforming systems.
ACM Trans. Embedded Comput. Syst., 2013

DeSyRe: On-demand system reliability.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Addressing GPU On-Chip Shared Memory Bank Conflicts Using Elastic Pipeline.
International Journal of Parallel Programming, 2013

High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Compiler-aided methodology for low overhead on-line testing.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Dataflow computing with Polymorphic Registers.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

FASTER run-time reconfiguration management.
Proceedings of the International Conference on Supercomputing, 2013

An improved system approach towards future cochlear implants.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Separable 2D Convolution with Polymorphic Register Files.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems.
The Journal of Supercomputing, 2012

On improved MANET network utilization.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2012

Architecture-level fault-tolerance for biomedical implants.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

On implementability of Polymorphic Register Files.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Implementation Study of FFT on Multi-lane Vector Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

The DeSyRe Project: On-Demand System Reliability.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Scalability Study of Polymorphic Register Files.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
Multi-Core Platforms for Beamforming and Wave Field Synthesis.
IEEE Trans. Multimedia, 2011

Exploiting SPMD Horizontal Locality.
Computer Architecture Letters, 2011

Vector processor customization for FFT.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

4-D parity codes for soft error correction in aerospace applications.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Welcome to ICCD 2011!
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Reconfigurable acceleration and dynamic partial self-reconfiguration in general purpose computing.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Compatibility Study of Compile-Time Optimizations for Power and Reliability.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

HMMER Performance Model for Multicore Architectures.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Scaling HMMER Performance on Multicore Architectures.
Proceedings of the International Conference on Complex, 2011

Parametrizing multicore architectures for multiple sequence alignment.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Elastic pipeline: addressing GPU on-chip shared memory bank conflicts.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Scalability Evaluation of a Polymorphic Register File: A CG Case Study.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

A Reconfigurable Audio Beamforming Multi-Core Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
The SARC Architecture.
IEEE Micro, 2010

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism.
J. Electronic Testing, 2010

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

ImpBench revisited: An extended characterization of implant-processor benchmarks.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Polymorphic Register File for matrix operations.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

SAMS multi-layout memory: providing multiple views of data to boost SIMD performance.
Proceedings of the 24th International Conference on Supercomputing, 2010

Welcome to ICCD 2010!
Proceedings of the 28th International Conference on Computer Design, 2010

Fine-grain fault diagnosis for FPGA logic blocks.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Minimalistic architecture for reconfigurable audio Beamforming.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A novel HDL coding style to reduce power consumption for reconfigurable devices.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems.
Proceedings of the International Conference on Field-Programmable Technology, 2010

General Purpose Computing with Reconfigurable Acceleration.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A 3d-audio reconfigurable processor.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Low-cost, customized and flexible SRAM MBIST engine.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Using a CISC microcontroller to test embedded memories.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
Proceedings of the Design, Automation and Test in Europe, 2010

Memory testing with a RISC microcontroller.
Proceedings of the Design, Automation and Test in Europe, 2010

Scalability Analysis of Progressive Alignment on a Multicore.
Proceedings of the CISIS 2010, 2010

Challenges for embedded multicore architecture.
Proceedings of the 2010 International Conference on Compilers, 2010

ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices.
Proceedings of the Reconfigurable Computing: Architectures, 2010

A Modified Merging Approach for Datapath Configuration Time Reduction.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
High-bandwidth Address Generation Unit.
Signal Processing Systems, 2009

Introduction to the Special Issue on SAMOS 2007.
Signal Processing Systems, 2009

A reconfigurable beamformer for audio applications.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Reconfigurable Multithreading Architectures: A Survey.
Proceedings of the Embedded Computer Systems: Architectures, 2009

OpenMP extensions for FPGA accelerators.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Reconfigurable accelerator for WFS-based 3D-audio.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Data path Configuration Time Reduction for Run-time Reconfigurable Systems.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
Proceedings of the 2009 International Conference on Complex, 2009

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2009

Range Tries for scalable address lookup.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2008
Introduction to the Special Issue on Embedded Computing Systems for DSP.
Signal Processing Systems, 2008

Test Set Development for Cache Memory in Modern Microprocessors.
IEEE Trans. VLSI Syst., 2008

Cross-Layer Designs Architecture for LEO Satellite Ad Hoc Network.
Proceedings of the Wired/Wireless Internet Communications, 6th International Conference, 2008

Vectorized AES Core for High-throughput Secure Environments.
Proceedings of the High Performance Computing for Computational Science, 2008

ImpBench: A novel benchmark suite for biomedical, microelectronic implants.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2008

A self-adaptive on-line task placement algorithm for partially reconfigurable systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism.
Proceedings of the 13th European Test Symposium, 2008

Memory Organization with Multi-Pattern Parallel Accesses.
Proceedings of the Design, Automation and Test in Europe, 2008

Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

An efficient algorithm for free resources management on the FPGA.
Proceedings of the Design, Automation and Test in Europe, 2008

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Profiling of lossless-compression algorithms for a novel biomedical-implant architecture.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Profiling of symmetric-encryption algorithms for a novel biomedical-implant architecture.
Proceedings of the 5th Conference on Computing Frontiers, 2008

Low power microarchitecture with instruction reuse.
Proceedings of the 5th Conference on Computing Frontiers, 2008

Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices.
Proceedings of the Reconfigurable Computing: Architectures, 2008

Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Efficient Multicast Support in High-Speed Packet Switches.
JNW, 2007

Reverse Engineering Java Card Applets Using Power Analysis.
Proceedings of the Information Security Theory and Practices. Smart Cards, 2007

Optimizing Test Length for Soft Faults in DRAM Devices.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

High-Bandwidth Address Generation Unit.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Infrastructure for Cross-Layer Designs Interaction.
Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.
Proceedings of the FPL 2007, 2007

A Quantitative Prediction Model for Hardware/Software Partitioning.
Proceedings of the FPL 2007, 2007

HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.
Proceedings of the FPL 2007, 2007

Manifestation of Precharge Faults in High Speed DRAM Devices.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Real-time FPGA-implementation for blue-sky Detection.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Reconfigurable Universal Adder.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Multimedia rectangularly addressable memory.
IEEE Trans. Multimedia, 2006

SAD Prefetching for MPEG4 Using Flux Caches.
Proceedings of the Embedded Computer Systems: Architectures, 2006

A Platform for RFID Security and Privacy Administration (Awarded Best Paper!).
Proceedings of the 20th Conference on Systems Administration (LISA 2006), 2006

DRAM-Specific Space of Memory Tests.
Proceedings of the 2006 IEEE International Test Conference, 2006

FPGA accelerator for real-time skin segmentation.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

PISC: Polymorphic Instruction Set Computers.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Flux Caches: What Are They and Are They Useful?
Proceedings of the Embedded Computer Systems: Architectures, 2005

64-bit floating-point FPGA matrix multiplication.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

The Midlifekicker Microarchitecture Evaluation Metric.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
The MOLEN Polymorphic Processor.
IEEE Trans. Computers, 2004

The Molen Programming Paradigm.
Proceedings of the Computer Systems: Architectures, 2004

The Virtex II ProTM MOLEN Processor.
Proceedings of the Computer Systems: Architectures, 2004

Loading rho-µ-Code: Design Considerations.
Proceedings of the Computer Systems: Architectures, 2004

The State-of-Art and Future Trends in Testing Embedded Memories.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

The MOLEN Processor Prototype.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Visual Data Rectangular Memory.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

SCISM vs IA-64 Tagging: Differences/Code Density Effects.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

1997
March LA: a test for linked memory faults.
Proceedings of the European Design and Test Conference, 1997

1996
March LR: a test for realistic linked faults.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Realistic Linked Memory Cell Array Faults.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996


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