Alexandru Plesco

Orcid: 0000-0002-8250-1380

Affiliations:
  • ENS Lyon, France


According to our database1, Alexandru Plesco authored at least 8 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Data-aware process networks.
Proceedings of the CC '21: 30th ACM SIGPLAN International Conference on Compiler Construction, 2021

2017
Optimizing Affine Control With Semantic Factorizations.
ACM Trans. Archit. Code Optim., 2017

2012
FPGA-specific synthesis of loop-nests with pipelined computational cores.
Microprocess. Microsystems, 2012

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011
An FPGA architecture for solving the Table Maker's Dilemma.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Automatic Generation of FPGA-Specific Pipelined Accelerators.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators. (Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels).
PhD thesis, 2010

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


  Loading...