Alain Darte

According to our database1, Alain Darte authored at least 65 papers between 1991 and 2016.

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Bibliography

2016
Extended lattice-based memory allocation.
Proceedings of the 25th International Conference on Compiler Construction, 2016

2015
Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes.
Proceedings of the Compiler Construction - 24th International Conference, 2015

2013
Rank: A Tool to Check Program Termination and Computational Complexity.
Proceedings of the Sixth IEEE International Conference on Software Testing, 2013

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
SSI Properties Revisited.
ACM Trans. Embedded Comput. Syst., 2012

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011
Parallelism Detection in Nested Loops, Optimal.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Studying optimal spilling in the light of SSA.
Proceedings of the 14th International Conference on Compilers, 2011

A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs.
Proceedings of the Programming Languages and Systems - 9th Asian Symposium, 2011

2010
Parallel copy motion.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs.
Proceedings of the Static Analysis - 17th International Symposium, 2010

Understanding loops: The influence of the decomposition of Karp, Miller, and Winograd.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Introduction.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency.
Proceedings of the CGO 2009, 2009

2008
Advanced conservative and optimistic register coalescing.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Reservation table scheduling: branch-and-bound based optimization vs. integer linear programming techniques.
RAIRO - Operations Research, 2007

On the complexity of spill everywhere under SSA form.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

On the Complexity of Register Coalescing.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

Scheduling under resource constraints using dis-equations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
New Complexity Results on Array Contraction and Related Problems.
VLSI Signal Processing, 2005

A linear-time algorithm for optimal barrier placement.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005

Hardware/Software Interface for Multi-Dimensional Processor Arrays.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2003
Generalized multipartitioning of multi-dimensional arrays for parallelizing line-sweep computations.
J. Parallel Distrib. Comput., 2003

Lattice-based memory allocation.
Proceedings of the International Conference on Compilers, 2003

2002
Constructing and exploiting linear schedules with prescribed parallelism.
ACM Trans. Design Autom. Electr. Syst., 2002

Complexity of Multi-dimensional Loop Alignment.
Proceedings of the STACS 2002, 19th Annual Symposium on Theoretical Aspects of Computer Science, Antibes, 2002

Generalized Multipartitioning for Multi-Dimensional Arrays.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

New Results on Array Contraction.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Loop Parallelization Algorithms.
Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

2000
A Constructive Solution to the Juggling Problem in Processor Array Synthesis.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Temporary Arrays for Distribution of Loops with Control Dependences.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Scheduling the Computations of a Loop Nest with Respect to a Given Mapping.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Scheduling and automatic parallelization.
Birkhäuser, ISBN: 978-3-7643-4149-7, 2000

1999
Loop Shifting for Loop Compaction.
Proceedings of the Languages and Compilers for Parallel Computing, 1999

the NESTOR Library: A Tool for Implementing FORTRAN Source Transformations.
Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999

On the Complexity of Loop Fusion.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
Circuit Retiming Applied to Decomposed Software Pipelining.
IEEE Trans. Parallel Distrib. Syst., 1998

Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation.
Parallel Computing, 1998

On the Removal of Anti- and Output-Dependences.
International Journal of Parallel Programming, 1998

1997
Parallelizing Nested Loops with Approximations of Distance Vectors: A Survey.
Parallel Processing Letters, 1997

Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling.
Parallel Processing Letters, 1997

Plugging Anti and Output Dependence Removal Techniques Into Loop Parallelization Algorithm.
Parallel Computing, 1997

HPFIT: A Set of Integrated Tools for the Parallelization of Applications Using High Performance Fortran. PART I: HPFIT and the TransTOOL Environment.
Parallel Computing, 1997

On the Optimality of Allen and Kennedy's Algorithm for Parallelism Extraction in Nested Loops.
Parallel Algorithms Appl., 1997

1996
A New Guaranteed Heuristic for the Software Pipelining Problem.
Proceedings of the 10th international conference on Supercomputing, 1996

On the Optimality of Allen and Kennedy's Algorithm for Parallel Extraction in Nested Loops.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

On the Removal of Anti and Output Dependences.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

Optimal fine and medium grain parallelism detection in polyhedral reduced dependence graphs.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
Affine-by-Statement Scheduling of Uniform and Affine Loop Nests over Parametric.
J. Parallel Distrib. Comput., 1995

A characterization of one-to-one modular mappings.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Revisiting the Decomposition of Karp, Miller and Winograd.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
Constructive Methods for Scheduling Uniform Loop Nests.
IEEE Trans. Parallel Distrib. Syst., 1994

On the Alignment Problem.
Parallel Processing Letters, 1994

Mapping Uniform Loop Nests Onto Distributed Memory Architectures.
Parallel Computing, 1994

(Pen)-ultimate tiling?
Integration, 1994

Evaluating Array Expressions on Massively Parallel Machines with Communication/ Computation Overlap.
Proceedings of the Parallel Processing: CONPAR 94, 1994

1993
Mapping Uniform Loop Nests onto Distributed Memory Architectures.
Proceedings of the Parallel Computing: Trends and Applications, 1993

1992
Erratum to: Regular partitioning for synthesizing fixed-size systolic arrays.
Integration, 1992

1991
Linear Scheduling Is Nearly Optimal.
Parallel Processing Letters, 1991

Regular partitioning for synthesizing fixed-size systolic arrays.
Integration, 1991

Two heuristics for task scheduling.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991


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