Florent de Dinechin

Orcid: 0000-0003-4927-3301

According to our database1, Florent de Dinechin authored at least 89 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Towards Fixed-Point Formats Determination for Faust Programs.
CoRR, 2024

2023
Audio DSP to FPGA Compilation.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

Exact Fused Dot Product Add Operators.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022
Lossless Differential Table Compression for Hardware Function Evaluation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Computer Arithmetic: Continuing a Long and Steady Emergence.
Computer, 2022

A single-source C++20 HLS flow for function evaluation on FPGA and beyond.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Using integer linear programming for correctly rounded multipartite architectures.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Resource Optimal Squarers for FPGAs.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Low-precision logarithmic arithmetic for neural network accelerators.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021
Towards Arithmetic-Centered Filter Design.
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

Resource Optimal Truncated Multipliers for FPGAs.
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

2020
Application-Specific Arithmetic in High-Level Synthesis Tools.
ACM Trans. Archit. Code Optim., 2020

Next Generation Arithmetic for Edge Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Towards Hardware IIR Filters Computing Just Right: Direct Form I Case Study.
IEEE Trans. Computers, 2019

Guest Editors Introduction: Special Section on Computer Arithmetic.
IEEE Trans. Computers, 2019

Byte-Aware Floating-point Operations through a UNUM Computing Unit.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A type-safe arbitrary precision arithmetic portability layer for HLS tools.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Evaluating the Hardware Cost of the Posit Number System.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

Reflections on 10 Years of FloPoCo.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Karatsuba with Rectangular Multipliers for FPGAs.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

Handbook of Floating-Point Arithmetic (2nd Ed.).
Springer, ISBN: 978-3-319-76526-6, 2018

2017
Hardware Division by Small Integer Constants.
IEEE Trans. Computers, 2017

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT.
Circuits Syst. Signal Process., 2017

Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Automating the pipeline of arithmetic datapaths.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Computing floating-point logarithms with fixed-point operations.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
Hardware Implementations of Fixed-Point Atan2.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

Code Generators for Mathematical Functions.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2014
Sum-of-product architectures computing just right.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Floating-Point Exponentiation Units for Reconfigurable Computing.
ACM Trans. Reconfigurable Technol. Syst., 2013

On Ziv's rounding test.
ACM Trans. Math. Softw., 2013

Fixed-point trigonometric functions on FPGAs.
SIGARCH Comput. Archit. News, 2013

Arithmetic core generation using bit heaps.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Multiplication by Rational Constants.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Table-Based Division by Small Integer Constants.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Certifying the Floating-Point Implementation of an Elementary Function Using Gappa.
IEEE Trans. Computers, 2011

Designing Custom Arithmetic Data Paths with FloPoCo.
IEEE Des. Test Comput., 2011

An FPGA architecture for solving the Table Maker's Dilemma.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

The Arithmetic Operators You Will Never See in a Microprocessor.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

A mixed-precision fused multiply and add.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Multipliers for floating-point double precision and beyond on FPGAs.
SIGARCH Comput. Archit. News, 2010

LEMA: towards a language for reliable arithmetic.
ACM Commun. Comput. Algebra, 2010

Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Floating-point exponential functions for DSP-enabled FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Pipelined FPGA Adders.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Multiplicative Square Root Algorithms for FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Automatic generation of polynomial-based hardware architectures for function evaluation.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


2009
Large multipliers with fewer DSP blocks.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Generating high-performance custom floating-point pipelines.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Digital Arithmetic.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables.
Tech. Sci. Informatiques, 2008

Optimizing polynomials for floating-point implementation
CoRR, 2008

Certifying floating-point implementations using Gappa
CoRR, 2008

An FPGA-specific approach to floating-point accumulation and sum-of-products.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

When FPGAs are better at floating-point than microprocessors.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

FPGA-Based Computation of the Inductance of Coils Used for the Magnetic Stimulation of the Nervous System.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

Integer and floating-point constant multipliers for FPGAs.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic.
J. VLSI Signal Process., 2007

Parameterized floating-point logarithm and exponential functions for FPGAs.
Microprocess. Microsystems, 2007

Fast and correctly rounded logarithms in double-precision.
RAIRO Theor. Informatics Appl., 2007

Floating-Point Trigonometric Functions for FPGAs.
Proceedings of the FPL 2007, 2007

Return of the hardware floating-point elementary function.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

Matériel et logiciel pour l'évaluation de fonctions numériques :précision, performance et validation.
, 2007

2006
Assisted verification of elementary functions using Gappa.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
Outils pour une comparaison sans <i>a priori</i> entre arithmétique logarithmique et arithmétique flottante.
Tech. Sci. Informatiques, 2005

Multipartite Table Methods.
IEEE Trans. Computers, 2005

A Parameterized Floating-Point Exponential Function for FPGAs.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Table-based polynomials for fast hardware function evaluation.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Towards the Post-Ultimate libm.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Second Order Function Approximation Using a Single Multiplication on FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Software Carry-Save: A Case Study for Instruction-Level Parallelism.
Proceedings of the Parallel Computing Technologies, 2003

2002
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Some Improvements on Multipartite Table Methods .
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
The Price of Routing in FPGAs.
J. Univers. Comput. Sci., 2000

Constant Multipliers for FPGAs.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

1999
Towards Adaptable Hierarchical Placement for FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998
A Reconfigurable Engine for Real-Time Video Processing.
Proceedings of the Field-Programmable Logic and Applications, 1998

1997
Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms.
Proceedings of the Parallel Computing: Fundamentals, 1997

Libraries of schedule-free operators in Alpha.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
A Regular VLSI Array for an Irregular Algorithm.
Proceedings of the Parallel Algorithms for Irregularly Structured Problems, 1996

Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
A Localized Parallel Sorting Algorithm and its Implementation.
Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995

1993
Analysis of Parallel Algorithms for a Shared Virtual Memory Computer.
Proceedings of the Parallel Computing: Trends and Applications, 1993


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