Amadeo de Gracia Herranz

According to our database, Amadeo de Gracia Herranz authored at least 7 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

An Ultra-Low-Power Flip-Flop With Near-Threshold Robust Operation and Redundant-Free Internal Clock Transitions.

Borja Gutiérrez De Cabiedes, Javier De Mena Pacheco, Amadeo de Gracia Herranz, Marisa López-Vallejo

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2025

Ultra-Narrow Current Pulses Measurement Using a Cost-Effective Instrumentation System.

Amadeo de Gracia Herranz, Borja Gutiérrez De Cabiedes, Javier De Mena Pacheco, Marisa López-Vallejo

Proceedings of the 40th Conference on Design of Circuits and Integrated Systems, 2025

2024

Drift Compensation in Multilevel PCM for in-Memory Computing Accelerators.

L. Pistolesi, Artem Glukhov, Amadeo de Gracia Herranz, Marisa López-Vallejo, Marcella Carissimi, Marco Pasotti, Pier Luigi Rolandi, Andrea Redaelli, I. Muñoz-Martín, S. Bianchi, Andrea Bonfanti, Daniele Ielmini

Proceedings of the IEEE International Reliability Physics Symposium, 2024

A Lightweight Analog RFID Front-End for Interfacing Sensors.

Javier De Mena Pacheco, Borja Gutiérrez De Cabiedes, Amadeo de Gracia Herranz, Marisa López-Vallejo

Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024

2021

Time to Digital Sensing for Multilevel RRAM Cells.

Amadeo de Gracia Herranz, Marisa López-Vallejo

IEEE Access, 2021

2020

Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations.

Amadeo de Gracia Herranz, Marisa López-Vallejo

Integr., 2020

2019

Temperature-aware writing architecture for multilevel memristive cells.

Amadeo de Gracia Herranz, Marisa López-Vallejo

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019