Pier Luigi Rolandi

According to our database1, Pier Luigi Rolandi authored at least 19 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2009
System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities.
IEEE J. Solid State Circuits, 2008

2007
A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile Memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A dynamically adaptive DSP for heterogeneous reconfigurable platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

3D Capacitive Interconnections for High Speed Interchip Communication.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Yield prediction for 3D capacitive interconnections.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2003
Power efficient charge pump in deep submicron standard CMOS technology.
IEEE J. Solid State Circuits, 2003

A high compliance CMOS current source for low voltage applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.
Proceedings of the 40th Design Automation Conference, 2003

2001
A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory.
IEEE J. Solid State Circuits, 2001

2000
A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
An analog associative memory chip for VQ image compression.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Analog sense amplifiers for high density NOR flash memories.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997
Words Recognition using Associative Memory.
Proceedings of the 4th International Conference Document Analysis and Recognition (ICDAR '97), 1997

1995
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995


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