Amir Kaivani

According to our database1, Amir Kaivani authored at least 14 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2014
Area Efficient Sequential Decimal Fixed-point Multiplier.
J. Signal Process. Syst., 2014

High-speed FFT processors based on redundant number systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Decimal Division Algorithms: The Issue of Partial Remainders.
J. Signal Process. Syst., 2013

Decimal SRT Square Root: Algorithm and Architecture.
Circuits Syst. Signal Process., 2013

Decimal signed digit addition using stored transfer encoding.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012
High-frequency sequential decimal multipliers.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Improving the speed of decimal division.
IET Comput. Digit. Tech., 2011

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.
Comput. J., 2011

2010
Fully redundant decimal addition and subtraction using stored-unibit encoding.
Integr., 2010

2009
Improving the Speed of Parallel Decimal Multiplication.
IEEE Trans. Computers, 2009

2007
Binary-coded decimal digit multipliers.
IET Comput. Digit. Tech., 2007

Reversible Barrel Shifters.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R.
Proceedings of the 9th International Conference in Information Technology, 2006


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