Ghassem Jaberipur

Orcid: 0000-0001-8458-7627

According to our database1, Ghassem Jaberipur authored at least 59 papers between 2005 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture.
Proceedings of the 25th IEEE International Symposium on a World of Wireless, 2025

2024
Modulo-(2<sup>2n</sup>+1) Arithmetic via Two Parallel n-bit Residue Channels.
CoRR, 2024

RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine.
IEEE Access, 2024

Sparse Matrix-Vector Multiplication Based on Online Arithmetic.
IEEE Access, 2024

Montgomery Modular Multiplication via Single-Base Residue Number Systems.
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024

2023
A Parallel Prefix Modulo-(2<sup>q</sup> + 2<sup>q-1</sup> + 1) Adder via Diminished-1 Representation of Residues.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Modulo-(2<sup>q</sup> - 3) Multiplication with Fully Modular Partial Product Generation and Reduction.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

2022
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels.
IEEE Trans. Computers, 2022

Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set.
Signal Image Video Process., 2022

2020
Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.
Microelectron. J., 2020

Complex exponential functions: A high-precision hardware realization.
Integr., 2020

Fast division in the residue number system {2<i><sup>n</sup></i> + 1, 2<i><sup>n</sup></i>, 2<i><sup>n</sup></i>-1} based on shortcut mixed radix conversion.
Comput. Electr. Eng., 2020

Majority-Logic, its applications, and atomic-scale embodiments.
Comput. Electr. Eng., 2020

2019
Impact of diminished-1 encoding on residue number systems arithmetic units and converters.
Comput. Electr. Eng., 2019

Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies.
IEEE Trans. Sustain. Comput., 2018

Extended Redundant-Digit Instruction Set for Energy-Efficient Processors.
ACM Trans. Embed. Comput. Syst., 2018

FIR Filter Realization via Deferred End-Around Carry Modular Addition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Radix-8 full adder in QCA with single clock-zone carry propagation delay.
Microprocess. Microsystems, 2017

Fast Energy Efficient Radix-16 Sequential Multiplier.
IEEE Embed. Syst. Lett., 2017

(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2<sup>n</sup>+1) unified adder/subtractor with full zero handling.
Comput. Electr. Eng., 2017

2016
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Fast low energy RNS comparators for 4-moduli sets {2<sup>n</sup>±1, 2<sup>n</sup>, m} with m∈{2<sup>n+1</sup>±1, 2<sup>n-1</sup>-1}.
Integr., 2016

Decimal Square Root: Algorithm and Hardware Implementation.
Circuits Syst. Signal Process., 2016

Decimal Goldschmidt: A hardware algorithm for radix-10 division.
Comput. Electr. Eng., 2016

Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding.
Comput. Electr. Eng., 2016

A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
(4+2 log n)ΔG Parallel Prefix Modulo-(2<sup>n</sup>-3) Adder via Double Representation of Residues in [0, 2].
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings".
IEEE Trans. Computers, 2015

A New Residue Number System with 5-Moduli Set: {2<sup>2<i>q</i></sup>, 2<sup><i>q</i></sup>±3, 2<sup><i>q</i></sup>±1}.
Comput. J., 2015

Modulo-(2<sup>n</sup> - 2<sup>q</sup> - 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2014
Low area/power decimal addition with carry-select correction and carry-select sum-digits.
Integr., 2014

A ROM-less reverse RNS converter for moduli set {2<sup>q</sup>±1, 2<sup>q</sup>±3}.
IET Comput. Digit. Tech., 2014

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers.
Circuits Syst. Signal Process., 2014

Double {0, 1, 2} representation modulo-(2<sup>n</sup> - 3) adders.
Proceedings of the International Conference on Systems, Signals and Image Processing, 2014

2012
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits.
IET Comput. Digit. Tech., 2012

Improved CMOS (4; 2) compressor designs for parallel multipliers.
Comput. Electr. Eng., 2012

2011
Improving the speed of decimal division.
IET Comput. Digit. Tech., 2011

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.
Comput. J., 2011

A Family of High Radix Signed Digit Adders.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

On building general modular adders from standard binary arithmetic components.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.
IEEE Trans. Computers, 2010

Fully redundant decimal addition and subtraction using stored-unibit encoding.
Integr., 2010

An improved maximally redundant signed digit adder.
Comput. Electr. Eng., 2010

2009
Improving the Speed of Parallel Decimal Multiplication.
IEEE Trans. Computers, 2009

A fully redundant decimal adder and its application in parallel decimal multipliers.
Microelectron. J., 2009

Unified Approach to the Design of Modulo-(2<sup>n</sup> +/- 1) Adders Based on Signed-LSB Representation of Residues.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

Fully Redundant Decimal Arithmetic.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
Constant-time addition with hybrid-redundant numbers: Theory and implementations.
Integr., 2008

A Nonspeculative Maximally Redundant Signed Digit Adder.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
Binary-coded decimal digit multipliers.
IET Comput. Digit. Tech., 2007

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic.
IET Circuits Devices Syst., 2007

2006
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.
J. VLSI Signal Process., 2006

2005
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005


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