Ghassem Jaberipur

Dariush Badri

Jeong-A Lee

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Modulo-(2q - 3) Multiplication with Fully Modular Partial Product Generation and Reduction.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

2022

Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations.

[BibT_eX]

[DOI]

Farzad Ghazanfari

IEEE Trans. Very Large Scale Integr. Syst., 2022

Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels.

[BibT_eX]

[DOI]

Zabihollah Ahmadpour

IEEE Trans. Computers, 2022

Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set.

[BibT_eX]

[DOI]

Signal Image Video Process., 2022

2020

Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$.

[BibT_eX]

[DOI]

Sina Bakhtavari Mamaghani

Bardia Nadimi

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.

[BibT_eX]

[DOI]

Mohammad Hossein Moaiyeri

Microelectron. J., 2020

Complex exponential functions: A high-precision hardware realization.

[BibT_eX]

[DOI]

Integr., 2020

Fast division in the residue number system {2n + 1, 2n, 2n-1} based on shortcut mixed radix conversion.

[BibT_eX]

[DOI]

Zeinab Torabi

Comput. Electr. Eng., 2020

Majority-Logic, its applications, and atomic-scale embodiments.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2020

2019

Impact of diminished-1 encoding on residue number systems arithmetic units and converters.

[BibT_eX]

[DOI]

Saeed Nejati

Comput. Electr. Eng., 2019

Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues.

[BibT_eX]

[DOI]

Sahar Moradi Cherati

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2018

Extended Redundant-Digit Instruction Set for Energy-Efficient Processors.

[BibT_eX]

[DOI]

Saba Amanollahi

ACM Trans. Embed. Comput. Syst., 2018

FIR Filter Realization via Deferred End-Around Carry Modular Addition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems.

[BibT_eX]

[DOI]

Saba Amanollahi

IEEE Trans. Very Large Scale Integr. Syst., 2017

Radix-8 full adder in QCA with single clock-zone carry propagation delay.

[BibT_eX]

[DOI]

Milad Sangsefidi

Microprocess. Microsystems, 2017

Fast Energy Efficient Radix-16 Sequential Multiplier.

[BibT_eX]

[DOI]

Saba Amanollahi

IEEE Embed. Syst. Lett., 2017

(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2017

2016

Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range.

[BibT_eX]

[DOI]

Zeinab Torabi

IEEE Trans. Very Large Scale Integr. Syst., 2016

Fast low energy RNS comparators for 4-moduli sets {2n±1, 2n, m} with m∈{2n+1±1, 2n-1-1}.

[BibT_eX]

[DOI]

Zeinab Torabi

Integr., 2016

Decimal Square Root: Algorithm and Hardware Implementation.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2016

Decimal Goldschmidt: A hardware algorithm for radix-10 division.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2016

Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding.

[BibT_eX]

[DOI]

Morteza Dorrigiv

Comput. Electr. Eng., 2016

A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements.

[BibT_eX]

[DOI]

Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015

(4+2 log n)ΔG Parallel Prefix Modulo-(2n-3) Adder via Double Representation of Residues in [0, 2].

[BibT_eX]

[DOI]

Seyed Hamed Fatemi Langroudi

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings".

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

A New Residue Number System with 5-Moduli Set: {22q, 2q±3, 2q±1}.

[BibT_eX]

[DOI]

HamidReza Ahmadifar

Seyed Hamed Fatemi Langroudi

Comput. J., 2015

Modulo-(2n - 2q - 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2014

Low area/power decimal addition with carry-select correction and carry-select sum-digits.

[BibT_eX]

[DOI]

Morteza Dorrigiv

Integr., 2014

A ROM-less reverse RNS converter for moduli set {2q±1, 2q±3}.

[BibT_eX]

[DOI]

HamidReza Ahmadifar

IET Comput. Digit. Tech., 2014

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers.

[BibT_eX]

[DOI]

Seyed Hamed Fatemi Langroudi

Reza Hashemi Asl

Circuits Syst. Signal Process., 2014

Double {0, 1, 2} representation modulo-(2n - 3) adders.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Systems, Signals and Image Processing, 2014

2012

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Improved CMOS (4; 2) compressor designs for parallel multipliers.

[BibT_eX]

[DOI]

Abdoreza Pishvaie

Ali Jahanian

Comput. Electr. Eng., 2012

2011

Improving the speed of decimal division.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.

[BibT_eX]

[DOI]

Comput. J., 2011

A Family of High Radix Signed Digit Adders.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

On building general modular adders from standard binary arithmetic components.

[BibT_eX]

[DOI]

Saeed Nejati

Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Fully redundant decimal addition and subtraction using stored-unibit encoding.

[BibT_eX]

[DOI]

Integr., 2010

An improved maximally redundant signed digit adder.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2010

2009

Improving the Speed of Parallel Decimal Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

A fully redundant decimal adder and its application in parallel decimal multipliers.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

Fully Redundant Decimal Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008

Constant-time addition with hybrid-redundant numbers: Theory and implementations.

[BibT_eX]

[DOI]

Integr., 2008

A Nonspeculative Maximally Redundant Signed Digit Adder.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Science and Engineering, 2008

2007

Binary-coded decimal digit multipliers.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2007

2006

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.

[BibT_eX]

[DOI]

Mohammad Ghodsi

J. VLSI Signal Process., 2006

2005

Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems.

[BibT_eX]

[DOI]