Andrea G. M. Cilio

According to our database1, Andrea G. M. Cilio authored at least 10 papers between 1999 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Hardware Cost Estimation for Application-Specific Processor Design.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Dictionary-based program compression on transport triggered architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Immediate optimization for compressed transport triggered architecture instructions.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation.
Proceedings of the Compiler Construction, 11th International Conference, 2002

2001
Code Positioning for VLIW Architectures.
Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001

2000
Link-time effective whole-program optimizations.
Future Gener. Comput. Syst., 2000

1999
A Linker for effective Whole-Program Optimization.
Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999

Floating Point to Fixed Point Conversion of C Code.
Proceedings of the Compiler Construction, 8th International Conference, 1999

A Programmable ANSI C Transformation Engine.
Proceedings of the Compiler Construction, 8th International Conference, 1999


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