Tommi Rantanen

According to our database1, Tommi Rantanen authored at least 3 papers between 2003 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Hardware Cost Estimation for Application-Specific Processor Design.
Proceedings of the Embedded Computer Systems: Architectures, 2005

2003
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Immediate optimization for compressed transport triggered architecture instructions.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003


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