Andreas Ehliar

According to our database1, Andreas Ehliar authored at least 11 papers between 2004 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Challenging the limits of FFT performance on FPGAs (Invited paper).
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
Low-complexity general FIR filters based on Winograd's inner product algorithm.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2009
An ASIC perspective on FPGA optimizations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4.
IET Comput. Digit. Tech., 2008

A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.
Proceedings of the FPL 2008, 2008

2007
An fpga based open source network-on-chip architecture.
Proceedings of the FPL 2007, 2007

2005
Flexible route lookup using range search.
Proceedings of the Third IASTED International Conference on Communications and Computer Networks, 2005

2004
Using low precision floating point numbers to reduce memory cost for MP3 decoding.
Proceedings of the IEEE 6th Workshop on Multimedia Signal Processing, 2004

Reduced floating point for MPEG1/2 layer III decoding.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004


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