Oscar Gustafsson
Orcid: 0000-0003-3470-3911
According to our database1,
Oscar Gustafsson
authored at least 136 papers
between 1999 and 2024.
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Bibliography
2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
Integer Linear Programming Modeling of Addition Sequences With Additional Constraints for Evaluation of Power Terms.
CoRR, 2023
Analyzing Step-Size Approximation for Fixed-Point Implementation of LMS and BLMS Algorithms.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the Forum on Specification & Design Languages, 2023
2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
2021
Massive Machine-Type Communication Pilot-Hopping Sequence Detection Architectures Based on Non-Negative Least Squares for Grant-Free Random Access.
IEEE Open J. Circuits Syst., 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Approximate Floating-Point Operations with Integer Units by Processing in the Logarithmic Domain.
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021
2020
Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems.
J. Signal Process. Syst., 2020
ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Pilot-Hopping Sequence Detection Architecture for Grant-Free Random Access using Massive MIMO.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
An Architecture for Grant-Free Random Access Massive Machine Type Communication Using Coordinate Descent.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Integr., 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
J. Signal Process. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
A Modular Base Station Architecture for Massive MIMO with Antenna and User Scalability per Processing Node.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Computation limited matrix inversion using Neumann series expansion for massive MIMO.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
IEEE Trans. Signal Process., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Impact of region-of-interest method on quantitative analysis of DTI data in the optic tracts.
BMC Medical Imaging, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Hardware architecture for positive definite matrix inversion based on LDL decomposition and back-substitution.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
Decimation filters for high-speed delta-sigma modulators with passband constraints: General versus CIC-based FIR filters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Filter-bank based all-digital channelizers and aggregators for multi-standard video distribution.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Generalized division-free architecture and compact memory structure for resampling in particle filters.
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain.
VLSI Design, 2014
Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Linear programming design of semi-digital FIR filter and ΣΔ modulator for VDSL2 transmitter.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
J. Electr. Comput. Eng., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
The Impact of Dynamic Voltage and Frequency Scaling on Multicore DSP Algorithm Design [Exploratory DSP].
IEEE Signal Process. Mag., 2011
Low-Complexity Constant Multiplication Based on Trigonometric Identities with Applications to FFTs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Electron. Express, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Minimum adder depth multiple constant multiplication algorithm for low power FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Finite wordlength properties of matrix inversion algorithms in fixed-point and logarithmic number systems.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication.
IEEE Signal Process. Lett., 2010
Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures.
Circuits Syst. Signal Process., 2010
Twiddle factor memory switching activity analysis of radix-2<sup>2</sup> and equivalent FFT algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Design of narrow-band and wide-band frequency-response masking filters using sparse non-periodic sub-filters.
Proceedings of the 18th European Signal Processing Conference, 2010
Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IET Comput. Digit. Tech., 2008
Comments on 'A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library'.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Power optimization of weighted bit-product summation tree for elementary function generator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Architecture-aware design of a decimation filter based on a dual wordlength multiply-accumulate unit.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Comparison of multiplierless implementation of nonlinear-phase versus linear-phase FIR filters.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Proceedings of the Arithmetic of Finite Fields, First International Workshop, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Linear-phase FIR interpolation, decimation, and mth-band filters utilizing the farrow structure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A low power decimation filter architecture for high-speed single-bit sigma-delta modulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Switching activity in bit-serial constant-coefficient multipliers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Mth-band linear-phase FIR filter interpolators and decimators utilizing the Farrow structure.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Multiplier blocks using carry-save adders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
J. Circuits Syst. Comput., 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Bit-level pipelinable general and fixed coefficient digit-serial/parallel multipliers based on shift-accumulation.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Narrow-band and wide-band high-speed recursive digital filters using single filter frequency masking techniques.
Proceedings of the Sixth International Symposium on Signal Processing and its Applications, 2001
Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Implementation of bit-parallel lattice wave digital filters with increased maximal sample rate.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Decreasing the minimal sample period for recursive filters implemented using distributed arithmetic.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Design and efficient implementation of high-speed narrow-band recursive digital filters using single filter frequency masking techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Design and efficient implementation of narrow-band single filter frequency masking FIR filters.
Proceedings of the 10th European Signal Processing Conference, 2000
1999
Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Maximally fast scheduling of bit-serial lattice wave digital filters using constrained third-order sections.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999