Dake Liu

According to our database1, Dake Liu authored at least 100 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2019
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G.
IEEE Trans. VLSI Syst., 2019

2018
Design Space Exploration of 1-D FFT Processor.
Signal Processing Systems, 2018

High-throughput bit processor for cryptography, error correction, and error detection.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding.
IEEE Access, 2018

2017
Computational Complexity Analysis of FEC Decoding on SDR Platforms.
Signal Processing Systems, 2017

Efficiency Enhancement for an Inductive Wireless Power Transfer System by Optimizing the Impedance Matching Networks.
IEEE Trans. Biomed. Circuits and Systems, 2017

An Adaptive Impedance Matching Network with Closed Loop Control Algorithm for Inductive Wireless Power Transfer.
Sensors, 2017

An NFC on Two-Coil WPT Link for Implantable Biomedical Sensors under Ultra-Weak Coupling.
Sensors, 2017

A Magnetic-Balanced Inductive Link for the Simultaneous Uplink Data and Power Telemetry.
Sensors, 2017

A 3-coil simultaneous power and uplink data transmission inductive link for battery-less implantable devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
A High-Throughput Processor for Cryptographic Hash Functions.
JCM, 2016

A digital crystal-less clock generation scheme for wireless biomedical implants.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
High-Throughput Trellis Processor for Multistandard FEC Decoding.
IEEE Trans. VLSI Syst., 2015

Virtual RATs and a flexible and tailored radio access network evolving to 5G.
IEEE Communications Magazine, 2015

Energy-Efficient Sorting with the Distributed Memory Architecture ePUMA.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Loop acceleration and instruction repeat support for application specific instruction-set processors.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A contention-free memory subsystem for 5G Turbo decoder with flexible degree of parallelism.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

High performance table-based architecture for parallel CRC calculation.
Proceedings of the 2015 IEEE International Workshop on Local and Metropolitan Area Networks, 2015

Software-based QPP interleaving for baseband DSPs with LUT-accelerated addressing.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Cost-efficient mapping of 3- and 5-point DFTs to general baseband processors.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

ePUMA: A processor architecture for future DSP.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Benefit and cost of cross sliding window scheduling for low latency 5G Turbo decoding.
Proceedings of the 2015 IEEE/CIC International Conference on Communications in China, 2015

Combined RF and multiphase PWM transmitter.
Proceedings of the European Conference on Circuit Theory and Design, 2015

An optimizing procedure of the wireless power transfer link for an intraocular implantable device.
Proceedings of the 8th International Conference on Biomedical Engineering and Informatics, 2015

A novel transcutaneous NFC uplink system symbiotic with inductive wireless power supply under ultra low coupling coefficient.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
A Vision of IoT: Applications, Challenges, and Opportunities With China Perspective.
IEEE Internet of Things Journal, 2014

Comprehensive Performance Analysis of Two-Way Multi-Relay System with Amplify-and-Forward Relaying.
IEICE Transactions, 2014

A conflict-free access method for parallel turbo decoder.
Proceedings of the Sixth International Conference on Wireless Communications and Signal Processing, 2014

Memory sharing techniques for multi-standard high-throughput FEC decoder.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Recognition of access patterns for DSP kernel codes.
Proceedings of the 2nd International Conference on Systems and Informatics, 2014

Matrix reordering techniques for memory conflict reduction for pipelined QC-LDPC decoder.
Proceedings of the 2014 IEEE/CIC International Conference on Communications in China, 2014

FPGA implementation of a multi-algorithm parallel FEC for SDR platforms.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Flexible multistandard FEC processor design with ASIP methodology.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Application Specific Instruction Set DSP Processors.
Proceedings of the Handbook of Signal Processing Systems, 2013

Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems.
IET Wireless Sensor Systems, 2013

Efficient sorting design on a novel embedded parallel computing architecture with unique memory access.
Computers & Electrical Engineering, 2013

Combined RF and multilevel PWM switch mode power amplifier.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Conflict-free data access for multi-bank memory architectures using padding.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

ePUMA: A unique memory access based parallel DSP processor for SDR and CR.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

2012
Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support.
Signal Processing Systems, 2012

Automatic Permutation for Arbitrary Static Access Patterns.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Automatic Synthesizable HDL Generator for NoGAP.
Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012

2011
Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio.
Signal Processing Systems, 2011

An Efficient Streaming Star Network for Multi-core Parallel DSP Processor.
Proceedings of the Second International Conference on Networking and Computing, 2011

Implementation Aspects of Channel Estimation for 3GPP LTE Terminals.
Proceedings of the European Wireless 2011, April 27-29, 2011, Vienna, Austria., 2011

Case Study of Efficient Parallel Memory Access Programming for the Embedded Heterogeneous Multicore DSP Architecture ePUMA.
Proceedings of the International Conference on Complex, 2011

A multi-level arbitration and topology free streaming network for chip multiprocessor.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

ePUMA embedded parallel DSP processor with Unique Memory Access.
Proceedings of the 8th International Conference on Information, 2011

2010
Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding.
Signal Processing Systems, 2010

Multimode Flex-Interleaver Core for Baseband Processor Platform.
Journal Comp. Netw. and Communic., 2010

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor.
IJERTCS, 2010

Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels.
IJERTCS, 2010

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless.
EURASIP J. Wireless Comm. and Networking, 2010

VLSI implementation of A multi-standard MIMO symbol detector for 3GPP LTE and WiMAX.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Automatic port and bus sizing in NoGap.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Operation Classification for Control Path Synthetization with NoGAP.
Proceedings of the Seventh International Conference on Information Technology: New Generations, 2010

Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

NoGapCL: A flexible common language for processor hardware description.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Application Specific Instruction Set DSP Processors.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Bridging dream and reality: Programmable baseband processors for software-defined radio.
IEEE Communications Magazine, 2009

Implementation Aspects of Fixed-Complexity Soft-Output MIMO Detection.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

NoGAP: A Micro Architecture Construction Framework.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An ASIC perspective on FPGA optimizations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Evaluation of MIMO symbol detectors for 3GPP LTE terminals.
Proceedings of the 17th European Signal Processing Conference, 2009

Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009

2008
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4.
IET Computers & Digital Techniques, 2008

Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008

Dual standard re-configurable hardware interleaver for turbo decoding.
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008

An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Implementation of a programmable linear MMSE detector for MIMO-OFDM.
Proceedings of the IEEE International Conference on Acoustics, 2008

A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.
Proceedings of the FPL 2008, 2008

2007
Area Efficient Fully Programmable Baseband Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Lattice-Reduction Aided Multi-User STBC Decoding with Resource Constraints.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Efficient Complex Matrix Inversion for MIMO Software Defined Radio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An fpga based open source network-on-chip architecture.
Proceedings of the FPL 2007, 2007

2006
MIPS cost estimation for OFDM-VBLAST systems.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2006

Accelerating CABAC encoding for multi-standard media with configurability.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms.
Proceedings of the ARCS 2006, 2006

2005
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A Low Area and Low Power Programmable Baseband Processor Architecture.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A programmable SIMD-based multi-standard Rake receiver architecture.
Proceedings of the 13th European Signal Processing Conference, 2005

Flexible route lookup using range search.
Proceedings of the Third IASTED International Conference on Communications and Computer Networks, 2005

2004
Network processors for access network (NP4AN): trends and challenges.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Using low precision floating point numbers to reduce memory cost for MP3 decoding.
Proceedings of the IEEE 6th Workshop on Multimedia Signal Processing, 2004

Network on Chip Simulations for Benchmarking.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Bit Memory Instructions for a General CPU.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Reduced floating point for MPEG1/2 layer III decoding.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
A converged hardware solution for FFT, DCT and Walsh transform.
Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Power optimized packet buffering in a protocol processor.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A general DSP processor at the cost of 23K gates and 1/2 a man-year design time.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Implementation of fast CRC calculation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Embedded Protocol Processor for Fast and Efficient Packet Reception.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002


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