Andres Amaya

According to our database1, Andres Amaya authored at least 12 papers between 2013 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2021
A digital phase-based on-fly offset compensation method for decision feedback equalisers.
IET Circuits Devices Syst., 2021

2020
An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Improving Low-Dropout Regulator Frequency Stability by Exploiting the Equivalent Series Resistor and Featuring an Adaptive Biasing Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Multi-Level Power-on Reset for Fine-Grained Power Management.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

A 0.007mm<sup>2</sup> 50mA Three-Stage Fully-Integrated Capacitor-Less Low-Dropout Regulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

On-Fly Offset-Correction Method for High-Speed Comparators using All-Digital Phase Measurement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Digital Offset Reduction Method for Dynamic Comparators Based on Phase Measurement.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Mitigating Row Hammer attacks based on dummy cells in DRAM.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017

2016
A digital offset correction method for high speed analog front-ends.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

DRAM row-hammer attack reduction using dummy cells.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2014
A robust to PVT variations low-voltage low-power current mirror.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
A robust to PVT fully-differential amplifier in 45nm SOI-CMOS technology.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013


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