Ckristian Duran

Orcid: 0000-0003-3746-8320

According to our database1, Ckristian Duran authored at least 25 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Unified PUF and Crypto Core Exploiting the Metastability in Latches.
Future Internet, 2022

ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3.
Cryptogr., 2022

A Unified NVRAM and TRNG in Standard CMOS Technology.
IEEE Access, 2022

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse.
IEEE Access, 2022

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.
IEEE Access, 2022

A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore.
Proceedings of the 19th International SoC Design Conference, 2022

2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.
IEEE Access, 2021

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications.
Proceedings of the 18th International SoC Design Conference, 2021

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3.
Proceedings of the 18th International SoC Design Conference, 2021

Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

AES Sbox Acceleration Schemes for Low-Cost SoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).
IEICE Electron. Express, 2020

Quick Boot of Trusted Execution Environment With Hardware Accelerators.
IEEE Access, 2020

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage.
IEEE Trans. Consumer Electron., 2019

A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018
Standard cell camouflage method to counter silicon reverse engineering.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2016
A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016


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