Javier Ardila

Orcid: 0000-0001-6331-3133

According to our database1, Javier Ardila authored at least 11 papers between 2016 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2021
A digital phase-based on-fly offset compensation method for decision feedback equalisers.
IET Circuits Devices Syst., 2021

2020
On the Cross-Correlation Based Loop Gain Adaptation for Bang-Bang CDRs.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

A Stable Physically Unclonable Function Based on a Standard CMOS NVR.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
An All-Thin-Devices Level Shifter in Standard-Cell Format for Auto Place-and-Route Flow.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

A Family of Compact Trim-Free CMOS Nano-Ampere Current References.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Novel Loop Gain Adaptation Method for Digital CDRs Based on the Cross-Correlation Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Stochastic resonance in bang-bang phase detector gain and the impact on CDR locking.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
A Digital Offset Reduction Method for Dynamic Comparators Based on Phase Measurement.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
On the impact of channel loss on CDR locking.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016


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