Wayne P. Burleson

According to our database1, Wayne P. Burleson authored at least 172 papers between 1991 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to integrated circuit design and signal processing".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2018
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence.
IEEE Trans. VLSI Syst., 2018

Efficient Erasable PUFs from Programmable Logic and Memristors.
IACR Cryptology ePrint Archive, 2018

Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.
CoRR, 2018

2017
CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Persistent Clocks for Batteryless Sensing Devices.
ACM Trans. Embedded Comput. Syst., 2016

Using Statistical Models to Improve the Reliability of Delay-Based PUFs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Invited - Who is the major threat to tomorrow's security?: you, the hardware designer.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing.
IEEE Trans. on Circuits and Systems, 2015

Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Security Evaluation and Enhancement of Bistable Ring PUFs.
IACR Cryptology ePrint Archive, 2015

PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management.
IACR Cryptology ePrint Archive, 2015

Virtual Proofs of Reality and their Physical Implementation.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

Security Evaluation and Enhancement of Bistable Ring PUFs.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015

Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015

Development of a Layout-Level Hardware Obfuscation Tool.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Reinforcement Learning for Thermal-aware Many-core Task Allocation.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Stealthy dopant-level hardware Trojans: extended version.
J. Cryptographic Engineering, 2014

Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware.
IACR Cryptology ePrint Archive, 2014

REFLEX: Reconfigurable logic for entropy extraction.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Dynamic synchronizer flip-flop performance in FinFET technologies.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Keynote talk I: Security and privacy in implantable medical devices: An ongoing concern.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Post-Silicon Validation and Calibration of Hardware Security Primitives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Variation Aware Design of Post-Silicon Tunable Clock Buffer.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Fine grained wearout sensing using metastability resolution time.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Predictive synchronization for DVFS-enabled multi-processor systems.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Hybrid modeling attacks on current-based PUFs.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Modeling and analysis of Phase Change Materials for efficient thermal management.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

On design of a highly secure PUF based on non-linear current mirrors.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware.
Proceedings of the 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2014

Hybrid side-channel/machine-learning attacks on PUFs: A new threat?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Efficient Power and Timing Side Channels for Physical Unclonable Functions.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

A lightweight cryptographic system for implantable biosensors.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.
IEEE Trans. VLSI Syst., 2013

PUF Modeling Attacks on Simulated and Silicon Data.
IEEE Trans. Information Forensics and Security, 2013

Power and Timing Side Channels for PUFs and their Efficient Exploitation.
IACR Cryptology ePrint Archive, 2013

PUF Modeling Attacks on Simulated and Silicon Data.
IACR Cryptology ePrint Archive, 2013

Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Efficient E-Cash in Practice: NFC-Based Payments for Public Transportation Systems.
Proceedings of the Privacy Enhancing Technologies - 13th International Symposium, 2013

Litho-aware and low power design of a secure current-based physically unclonable function.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Low-power Networks-on-Chip: Progress and remaining challenges.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

On-chip lightweight implementation of reduced NIST randomness test suite.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Balancing security and utility in medical devices?
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Stealthy Dopant-Level Hardware Trojans.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

2012
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees.
IEEE Trans. VLSI Syst., 2012

Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications.
IEEE Trans. Information Forensics and Security, 2012

Detecting Software Theft in Embedded Systems: A Side-Channel Approach.
IEEE Trans. Information Forensics and Security, 2012

An architecture-independent instruction shuffler to protect against side-channel attacks.
TACO, 2012

Fully Integrated Biochip Platforms for Advanced Healthcare.
Sensors, 2012

Side channels as building blocks.
J. Cryptographic Engineering, 2012

TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks.
Proceedings of the 21th USENIX Security Symposium, Bellevue, WA, USA, August 8-10, 2012, 2012

DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2012

Privacy Preserving Payments on Computational RFID Devices with Application in Intelligent Transportation Systems.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2012

PHAP: Password based Hardware Authentication using PUFs.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

The combined effect of process variations and power supply noise on clock skew and jitter.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Collaborative calibration of on-chip thermal sensors using performance counters.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Distributed sensor data processing for many-cores.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Design challenges for secure implantable medical devices.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A Dedicated Monitoring Infrastructure for Multicore Processors.
IEEE Trans. VLSI Syst., 2011

Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies.
J. Low Power Electronics, 2011

A 12.4μm2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Implementing hardware Trojans: Experiences from a hardware Trojan challenge.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

An arbiter based on-chip droop detector system.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Robust signaling techniques for through silicon via bundles.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Hardware security in VLSI.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
Calibration of on-chip thermal sensors using process monitoring circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Low-power sub-threshold design of secure physical unclonable functions.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Entropy Extraction in Metastability-based TRNG.
Proceedings of the HOST 2010, 2010

Thermal-aware voltage droop compensation for multi-core architectures.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Circuit-level NBTI macro-models for collaborative reliability monitoring.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Multicore soft error rate stabilization using adaptive dual modular redundancy.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers.
IEEE Trans. Computers, 2009

A security approach for off-chip memory in embedded microprocessor systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Temperature effects on energy optimization in sub-threshold circuit design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

On temperature planarization effect of copper dummy fills in deep nanometer technology.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

MOLES: Malicious off-chip leakage enabled by side-channels.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A monitor interconnect and support subsystem for multicore processors.
Proceedings of the Design, Automation and Test in Europe, 2009

Analysis and mitigation of process variation impacts on Power-Attack Tolerance.
Proceedings of the 46th Design Automation Conference, 2009

Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. VLSI Syst., 2008

Temperature measurement in Content Addressable Memory cells using bias-controlled VCO.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Low-power clock distribution in a multilayer core 3d microprocessor.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects.
IEEE Trans. VLSI Syst., 2007

Low power on-chip thermal sensors based on wires.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Thermal Impacts on NoC Interconnects.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Distributed Collaborative Adaptive Sensing: A Unifying Theme for a Junior Level Embedded Systems Course.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Dynamically configurable security for SRAM FPGA bitstreams.
IJES, 2006

A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Reconfigurable Security Support for Embedded Systems.
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006

2005
Power-Aware 3D Computer Graphics Rendering.
VLSI Signal Processing, 2005

A reconfigurable, power-efficient adaptive Viterbi decoder.
IEEE Trans. VLSI Syst., 2005

An energy-aware active smart card.
IEEE Trans. VLSI Syst., 2005

Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test.
IEEE Trans. Computers, 2005

Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Configurable Computing for High-Security/High-Performance Ambient Systems.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Sensing Design Issues in Deep Submicron CMOS SRAMs.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Jitter in Deep Sub-Micron Interconnect.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.
VLSI Signal Processing, 2004

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
IEEE Trans. VLSI Syst., 2004

Differential current-sensing for on-chip interconnects.
IEEE Trans. VLSI Syst., 2004

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Dynamically Configurable Security for SRAM FPGA Bitstreams.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Mitigating static power in current-sensed interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s.
Proceedings of the 2004 Design, 2004

2003
Using System On-A-Chip As A Vehicle For VLSI Design Education.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Interconnect Effort - A Unification of Repeater Insertion and Logical Effort.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Targeting Tiled Architectures in Design Exploration.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.
Proceedings of the 2003 International Conference on Image Processing, 2003

A hybrid adiabatic content addressable memory for ultra low-power applications.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Repeater and current-sensing hybrid circuits for on-chip interconnects.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Trading off Reliability and Power-Consumption in Ultra-low Power Systems.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A dynamically reconfigurable adaptive viterbi decoder.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001
Reconfigurable Computing for Digital Signal Processing: A Survey.
VLSI Signal Processing, 2001

Guest Editorial: Reconfigurable Signal Processing Systems.
VLSI Signal Processing, 2001

Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power.
Proceedings of the IEEE International Conference on Acoustics, 2001

Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT.
Proceedings of the 2nd International Workshop on Digital and Computational Video (DCV 2001), 2001

2000
Guest Editor's Introduction.
VLSI Signal Processing, 2000

Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

1999
The spring scheduling coprocessor: a scheduling accelerator.
IEEE Trans. VLSI Syst., 1999

Power Modelling in Field Programmable Gate Arrays (FPGA).
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998
Performance optimization of wireless local area networks through VLSI data compression.
Wireless Networks, 1998

Vlsi Array Architectures for Pyramid Vector Quantization.
VLSI Signal Processing, 1998

Guest Editors' Introduction.
VLSI Signal Processing, 1998

Efficient VLSI for Lempel-Ziv compression in wireless data communication networks.
IEEE Trans. VLSI Syst., 1998

Wave-pipelining: a tutorial and research survey.
IEEE Trans. VLSI Syst., 1998

Reconfiguration for power saving in real-time motion estimation.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
Low-power encodings for global communication in CMOS VLSI.
IEEE Trans. VLSI Syst., 1997

VLSI array algorithms and architectures for RSA modular multiplication.
IEEE Trans. VLSI Syst., 1997

An FPGA-based data acquisition system for a 95 GHz W-band radar.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996
Two dimensional codes for low power.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Bus-invert coding for low-power I/O.
IEEE Trans. VLSI Syst., 1995

High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Coding a terminated bus for low power.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Analog VLSI for robot path planning.
VLSI Signal Processing, 1994

A VLSI Systolic Array Architecture for Lempel-Ziv-Based Data Compression.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Forum: Wave-pipelining: Is it Practical?
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Using Regular Array Methods for DSP Module Synthesis.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

Distributed control synthesis for data-dependent iterative algorithms.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
The Spring Scheduling Co-Processor: Design, Use, and Performance.
Proceedings of the Real-Time Systems Symposium. Raleigh-Durham, NC, USA, December 1993, 1993

Rank-order Filtering Algorithms: A Comparison of VLSI Implementations.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

The Spring Scheduling Co-Processor: A Scheduling Accelerator.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1991
A VLSI design methodology for distributed arithmetic.
VLSI Signal Processing, 1991

Input/Output Design for VLSI Array Architectures.
VLSI, 1991

A Simulator for General Purpose Optical Arrays.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991


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