Andrew Pan

Orcid: 0000-0001-9666-0254

According to our database1, Andrew Pan authored at least 3 papers between 2016 and 2017.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2017
Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2016


  Loading...