Saptadeep Pal

According to our database1, Saptadeep Pal authored at least 12 papers between 2014 and 2022.

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Bibliography

2022
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems.
CoRR, 2022

2021
Designing a 2048-Chiplet, 14336-Core Waferscale Processor.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Design Space Exploration for Chiplet-Assembly-Based Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Pathfinding for 2.5D interconnect technologies.
Proceedings of the SLIP '20: System-Level Interconnect, 2020

2019
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training.
IEEE Micro, 2019

Compression with multi-ECC: enhanced error resiliency for magnetic memories.
Proceedings of the International Symposium on Memory Systems, 2019

Architecting Waferscale Processors - A GPU Case Study.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
A Case for Packageless Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Advanced Packaging and Heterogeneous Integration to Reboot Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014
Cable length minimisation in long-reach-PON planning for sparsely populated areas.
Proceedings of the 18th International Conference on Optical Network Design and Modeling, 2014

FPGA implementation of stream cipher using Toeplitz Hash function.
Proceedings of the 2014 International Conference on Advances in Computing, 2014


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