Chi On Chui

According to our database, Chi On Chui authored at least 9 papers between 2005 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of two.

2016

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices.

Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits.

Greg Leung, Shaodi Wang, Andrew Pan, Puneet Gupta, Chi On Chui

IEEE Trans. Very Large Scale Integr. Syst., 2016

2013

Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation.

Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz

ACM J. Emerg. Technol. Comput. Syst., 2013

Nanowire field-programmable computing platform.

Santosh Khasanvis, Mostafizur Rahman, Prasad Shabadi, Pritish Narayanan, Hyung Suk Yu, Chi On Chui, Csaba Andras Moritz

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2011

Nanoscale Application Specific Integrated Circuits.

Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

2010

Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration.

Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Validating cascading of crossbar circuits with an integrated device-circuit exploration.

Pritish Narayanan, Csaba Andras Moritz, Kyoung-won Park, Chi On Chui

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

2006

Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs.

Hai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton

IEEE J. Solid State Circuits, 2006

2005

Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes.

Hai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005