Anju P. Johnson

Orcid: 0000-0002-7017-1644

According to our database1, Anju P. Johnson authored at least 24 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



Predicting Drug Review Polarity Using the Combination Model of Multi-Sense Word Embedding and Fuzzy Latent Dirichlet Allocation (FLDA).
IEEE Access, 2023

New Avenues for Automated Railway Safety Information Processing in Enterprise Architecture: An NLP Approach.
IEEE Access, 2023

LoRa-PUF: A Two-Step Security Solution for LoRaWAN.
Proceedings of the 97th IEEE Vehicular Technology Conference, 2023

Bio-Inspired Approaches to Safety and Security in IoT-Enabled Cyber-Physical Systems.
Sensors, 2020

Hardware-Intrinsic Multi-Layer Security: A New Frontier for 5G Enabled IIoT.
Sensors, 2020

Document Processing: Methods for Semantic Text Similarity Analysis.
Proceedings of the International Conference on INnovations in Intelligent SysTems and Applications, 2020

Exploring Self-Repair in a Coupled Spiking Astrocyte Neural Network.
IEEE Trans. Neural Networks Learn. Syst., 2019

Dynamic Multiparty Authentication using Cryptographic Hardware for the Internet of Things.
Proceedings of the 2019 IEEE SmartWorld, 2019

A Multi-layer Security Model for 5G-Enabled Industrial Internet of Things.
Proceedings of the Smart City and Informatization - 7th International Conference, 2019

Autonomous Learning Paradigm for Spiking Neural Networks.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019

Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018

FPGA-based Fault-injection and Data Acquisition of Self-repairing Spiking Neural Network Hardware.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications.
Microprocess. Microsystems, 2017

Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Self-repairing Learning Rule for Spiking Astrocyte-Neuron Networks.
Proceedings of the Neural Information Processing - 24th International Conference, 2017

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2017

An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications.
IEEE Trans. Multi Scale Comput. Syst., 2015

A Novel Attack on a FPGA based True Random Number Generator.
Proceedings of the 10th Workshop on Embedded Systems Security, 2015

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014