Rajat Subhra Chakraborty
Orcid: 0000-0003-3588-163X
According to our database1,
Rajat Subhra Chakraborty
authored at least 133 papers
between 2007 and 2024.
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Bibliography
2024
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency.
Integr., March, 2024
2023
J. Hardw. Syst. Secur., December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Image splicing detection with principal component analysis generated low-dimensional homogeneous feature set based on local binary pattern and support vector machine.
Multim. Tools Appl., July, 2023
Birds of the Same Feather Flock Together: A Dual-Mode Circuit Candidate for Strong PUF-TRNG Functionalities.
IEEE Trans. Computers, June, 2023
Deep Learning for Computational Problems in Hardware Security - Modeling Attacks on Strong Physically Unclonable Function Circuits
Studies in Computational Intelligence 1052, Springer, ISBN: 978-981-19-4016-3, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Theoretical Enumeration of Deployable Single-Output Strong PUF Instances Based on Uniformity and Uniqueness Constraints.
Proceedings of the Information Systems Security - 19th International Conference, 2023
2022
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT.
ACM Trans. Design Autom. Electr. Syst., 2022
Correlation Integral-Based Intrinsic Dimension: A Deep-Learning-Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention.
J. Cryptogr. Eng., 2022
Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators.
IEEE Embed. Syst. Lett., 2022
DIP Learning on CAS-Lock: Using Distinguishing Input Patterns for Attacking Logic Locking.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Linear and Non-Linear Filter-based Counter-Forensics Against Image Splicing Detection.
Proceedings of the Computer Vision and Image Processing - 7th International Conference, 2022
Proceedings of First Asian Symposium on Cellular Automata Technology, 2022
Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow.
Behavioral Synthesis for Hardware Security, 2022
2021
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability.
ACM Trans. Design Autom. Electr. Syst., 2021
IEEE Trans. Inf. Forensics Secur., 2021
A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices.
IET Comput. Digit. Tech., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT.
ACM Trans. Design Autom. Electr. Syst., 2020
IEEE Trans. Circuits Syst. Video Technol., 2020
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure.
J. Hardw. Syst. Secur., 2020
IEEE Des. Test, 2020
Stupify: A Hardware Countermeasure of KRACKs in WPA2 using Physically Unclonable Functions.
Proceedings of the Companion of The 2020 Web Conference 2020, 2020
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020
2019
Recycled and Remarked Counterfeit Integrated Circuit Detection by Image-Processing-Based Package Texture and Indent Analysis.
IEEE Trans. Ind. Informatics, 2019
Building PUF Based Authentication and Key Exchange Protocol for IoT Without Explicit CRPs in Verifier Database.
IEEE Trans. Dependable Secur. Comput., 2019
A Robust Residual Dense Neural Network For Countering Antiforensic Attack on Median Filtered Images.
IEEE Signal Process. Lett., 2019
J. Hardw. Syst. Secur., 2019
IACR Cryptol. ePrint Arch., 2019
ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
Revisiting the Security of LPN Based RFID Authentication Protocol and Potential Exploits in Hardware Implementations.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Classification of Computer Generated and Natural Images based on Efficient Deep Convolutional Recurrent Attention Model.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2019
Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR APUF.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019
2018
IEEE Trans. Computers, 2018
A Hardware Trojan Attack on FPGA-Based Cryptographic Key Generation: Impact and Detection.
J. Hardw. Syst. Secur., 2018
IEEE Embed. Syst. Lett., 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Discrete Cosine Transform Residual Feature Based Filtering Forgery and Splicing Detection in JPEG Images.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2018
2017
Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test.
ACM Trans. Design Autom. Electr. Syst., 2017
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.
IEEE Trans. Emerg. Top. Comput., 2017
ACM Trans. Embed. Comput. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Binary Decision Diagram Assisted Modeling of FPGA-Based Physically Unclonable Function by Genetic Programming.
IEEE Trans. Computers, 2017
Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications.
Microprocess. Microsystems, 2017
PUF+IBE: Blending Physically Unclonable Functions with Identity Based Encryption for Authentication and Key Exchange in IoTs.
IACR Cryptol. ePrint Arch., 2017
Proceedings of the 2017 IEEE International Conference on Multimedia & Expo Workshops, 2017
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Camera Source Identification Using Discrete Cosine Transform Residue Features and Ensemble Classifier.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2017
2016
A Technique to Evaluate Upper Bounds on Performance of Pixel-prediction Based Reversible Watermarking Algorithms.
J. Signal Process. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems.
IACR Cryptol. ePrint Arch., 2016
Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA.
IACR Cryptol. ePrint Arch., 2016
IACR Cryptol. ePrint Arch., 2016
Exploiting Safe Error based Leakage of RFID Authentication Protocol using Hardware Trojan Horse.
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Optimal Distortion Estimation for Prediction Error Expansion Based Reversible Watermarking.
Proceedings of the Digital Forensics and Watermarking - 15th International Workshop, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
IEEE Trans. Multi Scale Comput. Syst., 2015
ACM Trans. Embed. Comput. Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Improved Test Pattern Generation for Hardware Trojan Detection using Genetic Algorithm and Boolean Satisfiability.
IACR Cryptol. ePrint Arch., 2015
Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the Information Systems Security - 11th International Conference, 2015
Proceedings of the 10th Workshop on Embedded Systems Security, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015
2014
Synthesis Lectures on Information Security, Privacy, and Trust, Morgan & Claypool Publishers, ISBN: 978-3-031-02342-2, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
Proceedings of the Cellular Automata, 2014
CRC Press, ISBN: 978-1-439-89583-2, 2014
2013
ACM Trans. Multim. Comput. Commun. Appl., 2013
IEEE Trans. Computers, 2013
IET Image Process., 2013
IEEE Des. Test, 2013
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration.
Comput. Electr. Eng., 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
2012
IEEE Des. Test Comput., 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Research in Applied Computation Symposium, 2012
Proceedings of the Information Systems Security, 8th International Conference, 2012
2011
J. Electron. Test., 2011
Proceedings of the Security Aspects in Information Technology, 2011
Reversible Watermarking Using Priority Embedding through Repeated Application of Integer Wavelet Transform.
Proceedings of the Security Aspects in Information Technology, 2011
Proceedings of the Information Systems Security - 7th International Conference, 2011
Proceedings of the HOST 2011, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
System level self-healing for parametric yield and reliability improvement under power bound.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A study of asynchronous design methodology for robust CMOS-nano hybrid system design.
ACM J. Emerg. Technol. Comput. Syst., 2009
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping.
IET Comput. Digit. Tech., 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007