Arch Zaliznyak

According to our database, Arch Zaliznyak authored at least 3 papers between 1999 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Chip Package Co-design and Physical Verification for Heterogeneous Integration.

Rajsaktish Sankaranarayanan, Archanna Srinivasan, Arch Zaliznyak, Sreelekha Mittai

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2005

Multi-protocol embedded PCS IP in a FPGA-SOC.

Ramanand Venkata, Vinson Chan, Binh Ton, Chong Lee, Huy Ngo, Malik Kabani, Tam Nguyen, Arch Zaliznyak, Ning Xue, Steven Shen, Michael Zheng, Michael Lai, Steve Park, Lana Chan, Divya Vijayaraghavan, John Lam, Rakesh H. Patel

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1999

A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters.

Paul T. Sasaki, Yogendra Bobra, Warren E. Cory, Atul V. Cihia, Suresh M, Menon, Madhavi Kola, Mammen Thomas, Prasad Rau, Arch Zaliznyak

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999